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FS6159-01

Auxiliary Motherboard Clock Generator/Buffer IC

AMI Semiconductor 

FS6159-01

Auxiliary Motherboard Clock Generator/Buffer IC

4.0 Power Management

It is expected that the clock management inputs and the

register settings will be configured on power-up and will

not change during normal operation.

4.1 Clock Enable

Certain clock outputs may be disabled via either a

1. combination of logic states on the SEL_Q, SEL_R,

and SEL_S clock management control input pins as

shown in Table 4, or

2. the SMBus register bits, as shown in Section 3.3.

Disabling a clock, as determined by the clock manage-

ment control inputs, will override any SMBus register set-

ting.

Any active output, as determined by the clock manage-

ment control inputs, can be disabled at any time by the

SMBus register.

To enable a clock output, both the control inputs and the

SMBus register bits must by set appropriately. Enabled

clocks will continue to run while disabled clocks are

stopped. Note that if clocks are disabled while active,

glitches can occur.

4.2 Power Down

The PWR_DWN# signal is an asynchronous, active-low

LVTTL input that places the device in a low power inac-

tive state without removing power from the device. All

internal clocks are turned off, and all clock outputs are

held low.

The reference clocks for this device are developed by a

reference clock device (FS6158). It is assumed that the

PWR_DWN# signal is the same signal for both devices

Since PWR_DWN# is asynchronous, the signal is syn-

chronized internally to the falling edge of each individual

clock as shown in Figure 4. Each clock stops immediately

on its first falling edge after PWR_DWN#.

Once powered down, both the SDA and SCL inputs are

tristated. All register data is retained.

Table 13: Latency Table

SIGNAL

PWR_

DWN#

SIGNAL

STATE

0

Power

OFF

1

Power

ON

Output:

Device:

LATENCY

MIN.

MAX.

0 clocks

0 clocks

1 clock

1 REF clock

3ms

Upon the release of PWR_DWN# (power-up), external

circuitry should allow a minimum of 3ms for the PLL to

lock before enabling any clocks.

Figure 4: PWR_DWN# Timing

Any Clock

(internal)

PWR_DWN#

Any Clock

(output)

After REF

outputs shut off...

3ms until clock is valid

VCO

Crystal

Oscillator

Shaded regions in the Crystal Oscillator and VCO waveforms indicate that the clock is valid and the Crystal Oscillator and VCO are active.

ISO9001

6

2.27.02

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