R1LV1616H-I Ver la hoja de datos (PDF) - Renesas Electronics

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R1LV1616H-I

Wide Temperature Range Version 16 M SRAM (1-Mword × 16-bit / 2-Mword × 8-bit)

Renesas Electronics 

R1LV1616H-I Series

Low VCC Data Retention Characteristics

(Ta = −40 to +85°C)

Parameter

Symbol Min

Typ

Max

Unit Test conditions*2, 3

VCC for data retention

Data retention -4SI

current

-5SI

-4LI

VDR

1.5

ICCDR



ICCDR





3.6

0.5*1 8

0.5*1 25

V

Vin ≥ 0 V

(1) 0 V ≤ CS2 ≤ 0.2 V or

(2) CS2 ≥ VCC − 0.2 V,

CS1# ≥ VCC − 0.2 V or

(3) LB# = UB# ≥ VCC − 0.2 V,

CS2 ≥ VCC − 0.2 V,

CS1# ≤ 0.2 V

µA

VCC = 3.0 V, Vin ≥ 0 V

(1) 0 V ≤ CS2 ≤ 0.2 V or

(2) CS2 ≥ VCC − 0.2 V,

CS1# ≥ VCC − 0.2 V or

µA

(3) LB# = UB# ≥ VCC − 0.2 V,

CS2 ≥ VCC − 0.2 V,

CS1# ≤ 0.2 V

Average value

Chip deselect to data

retention time

tCDR

0





ns

See retention waveforms

Operation recovery time

tR

5





ms

Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and not guaranteed.

2. BYTE# ≥ VCC − 0.2 V or BYTE# ≤ 0.2 V

3. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB#, UB# buffer and Din

buffer. If CS2 controls data retention mode, Vin levels (address, WE#, OE#, CS1#, LB#, UB#,

I/O) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be

CS2 ≥ VCC − 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The other input levels (address, WE#, OE#, LB#, UB#,

I/O) can be in the high impedance state.

Rev.1.01, Nov.18.2004, page 18 of 19

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