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SD4842P67K65 Ver la hoja de datos (PDF) - Unspecified

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SD4842P67K65 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
SD4840/4841/4842/4843/4844
3. Frequency Jitter
The oscillation frequency is kept changed for low EMI and decreasing radiation on one frequency. The oscillation
frequency changes within a very small range to simplify EMI design. The rule of frequency changing: change
from 65KHz to 69KHz.
4. Light Load Mode
Working in this mode to reduce power dissipation. It works normally when FB is 500mV above and during
350mV<FB <500mV, there are two different conditions: when FB changes from low to high, there is no action for
switch and it is the same with condition of FB lower than 350mV; the other is that FB changes form high to low,
comparison value is increased for increasing turning on time to decrease switch loss.
For this mode, during FB changes form high to low, the output voltage increases (increasing speed is decided
by load) because of the high comparison value to decrease FB until it is 350mV below; when FB <350mV, there
is no action for switch and output voltage decrease (decreasing speed is also decided by load) to increase FB.
This is repeated to decrease action of switch for lower power dissipation.
5. Leading Edge Blanking
For this current-controlled circuit, there is pulse peak current during the transient of switch turning on and there is
an error operation if the current is sampled during this time. And leading edge blanking is adopted to eliminate
this error operation. The output of PWM comparator is used for controlling shutdown after the leading edge
blanking if there is any output drive.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: //www.silan.com.cn
REV:1.2 2008.12.17
Page 7 of 11

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