SC2596 Ver la hoja de datos (PDF) - Unspecified

Número de pieza

componentes Descripción

Fabricante

SC2596

Low Voltage Integrated DDR Termination Regulator

Unspecified 

SC2596

POWER MANAGEMENT

Pin Descriptions

Pin #

Pin Name

Pin Function

1

GND Ground.

2

EN Enable pin. SC2596 is disabled when EN pin is low.

3

VSENSE VSENSE pin is a feedback pin. Connect a 10nF to 100nF Ceramic capacitor

between this pin to ground and place this capacitor close to VSENSE pin is

required to avoid oscillation during transient condition.

4

VREF VREF pin is an output pin, which provides the buffered output of the internal

reference voltage. A 100nF ceramic capacitor should be connected from

VREF pin to ground with short trace.

5

VDDQ The VDDQ pin is an input pin for creating internal reference voltage to

regulate VTT. The VDDQ voltage is connected to an internal resistor divider.

The central tap of resistor divider (VDDQ/2) is connected to the internal

voltage buffer, which output is connected to VREF pin and the non-inverting

input of the error amplifier as the reference voltage. With the feedback loop

closed, the V TT output voltage will always track the VDDQ/2 precisely. It is

recommended that a 1uF ceramic capacitor should be added next to the

VDDQ pin to ground to increase the noise immunity.

6

AVCC The AVCC pin is used to supply all of the internal control circuitry. The AVCC

voltage has to be greater than its UVLO threshold voltage (2.1V typical) to

allow the SC2596 to be in normal operation. If AVCC voltage is lower than

the UVLO threshold voltage, the VTT pin should be in high impedance

status.

7

PVCC The PVCC pin provides the rail voltage from where the VTT pin draws load

current. There is a limitation between AVCC and PVCC. The PVCC voltage must

be less or equal to AVCC voltage to ensure the correct output voltage regulation.

The VTT source current capability is dependent on PVCC voltage. Higher the

voltage on PVCC, higher the source current.

8

VTT The VTT pin is the output of SC2596. It can sink and source continuous current

while keeping excellent load regulation. It is recommended that one should

use at least one 220uF low ESR capacitor and a 1uF ceramic capacitor or

one 220uF high ESR electrolytic capacitor and a 6.8uF ceramic capacitor,

which are placed on the VTT strip plane to ground reducing the voltage

spike under load transient condition.

THERMAL Pad for heatsinking purposes. Connect to ground plane using multiple vias.

PAD Not connected internally.

© 2007 Semtech Corp.

7

www.semtech.com

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