SC2596 Ver la hoja de datos (PDF) - Unspecified
Número de pieza
componentes Descripción
Fabricante
SC2596 Datasheet PDF : 13 Pages
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SC2596
POWER MANAGEMENT
Application Information (Cont.)
Application_2: Lower Power Loss Configuration for
SSTL-2
If power loss is a major concern, separating the PVCC
form AVCC and VDDQ will be a good choice (Figure 2).
The PVCC can operate at lower voltage (1.8V to 2.5V) if
2.5V voltage is applied on AVCC and the VDDQ, the source
current is lower due to the lower operating voltage ap-
plied on the PVCC.
EN
2.5V
VREF
1.25V
SC2596
1 GND
VTT 8
2 EN
PVCC 7
3 VSENSE AVCC 6
4 VREF
VDDQ 5
Cref
PVCC
2.5V
VDDQ
2.5V
VTT
1.25V
Cin2
Cin1 Cout
PRELIMINARY
Application_3: High Source Current Configuration
If there is a need for VTT to source more current, espe-
cially for DDR-II applications, the system designer can tie
the AVCC and PVCC to 3.3V while has the VDDQ tie to 1.
8V. This configuration can ensure more than 2A source
and sink capability from the VTT rail.
EN
VREF
0.9V
SC2596
1 GND
VTT 8
2
EN
7
PVCC
VTT
3.3V 0.9V
3 VSENSE
4 VREF
1M
10nF
Cref
100nF
AVCC 6
VDDQ
1.8V
VDDQ 5
Cin1 Cin2 Cout
1uF 100uF 220uF
10nF
100nF
1uF
100uF 220uF
0
Figure 4: High current set up for SSTL-18(DDR-II).
0
Figure 2: Lower power loss for SSTL-2(DDR-I).
Notes:
EN
VREF
0.9V
SC2596
1
GND
8
VTT
2 EN
PVCC 7
VTT
2.5V 0.9V
3
VSENSE
4 VREF
10nF
Cref
100nF
6
AVCC
VDDQ
1.8V
VDDQ 5
Cin1 Cin2 Cout
1uF 100uF 220uF
(a) The preferred configuration for DDR-I applications
is to tie AVCC and PVCC to VDDQ, which is typically 2.5V.
(b) If AVCC and PVCC rails are tied together, then the
VDDQ cannot lead the AVCC and PVCC.
0
Figure 3: Lower power loss for SSTL-18(DDR-II).
© 2007 Semtech Corp.
10
www.semtech.com
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