MN1030 Ver la hoja de datos (PDF) - Unspecified

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componentes Descripción

Fabricante

MN1030

MICROCOMPUTER

Unspecified 

■ Page Layouts

The three layouts below are the standards for the three Chapters.

Chapter 1 pages give the section title, an overview, the main text, and notes.

Chapter 2 pages give the instruction syntax, operational description, and notes.

Chapter 3 pages feature such items as pipeline operation diagrams, code samples, and notes.

Section title

Overview

(First page of section only)

Table Summary of

section contents

Notes Observe

these precautions to ensure

reliable program operation.

3 Instruction Functions

Chapter 1 Overview

The instruction set has been kept simple so that C compiler output is compact and highly optimized.

The following table shows all instructions divided into functional groups.

Data

Transfer

Instructions

Arithmetic

Instructions

Compare

Instructions

Bitwise Logical

Instructions

Bit Manipula-

tion Instructions

Shift

Instructions

Branch

Instructions

NOP Instruction

User Defined

Instructions

Transfer

Sign Extension

Clear

MOV

EXT

CLR

MOVBU

EXTB

MOVB*1

EXTB

MOVHU

EXTH

MOVH*1

EXTHU

MOVM

Addition

Subtraction

Multiplication

Division

ADD

SUB

MUL

DIV

ADDC

SUBC

MULU

DIVU

INC

INC4

Comparison

CMP

Logical Sum

Logical Product

Inversion

Exclusive OR

OR

AND

NOT

XOR

Test

Test and Set

Test and Clear

BTST

BSET

BCLR

Shift

Rotation

ASR*2

ROR

LSR*2

ROL

ASL

ASL2

Branch

Loop Setup

Subroutine Call

Return

Bcc

SETLB

CALL

RET

Lcc

CALLS

RETF

JMP

JSR*1

RETS

TRAP

RTS*1

RTI

No Operation

NOP

Expansion

UDFnn

UDFUnn

*1. MOVB, MOVH, and JSR are assembler shorthand for instruction sequences. RTS is an alias for RETS.

*2. The ASR Dn and LSR Dn variants are assembler shorthand for single-bit shifts of the specified register.

The BSET and BCLR instructions temporarily disable interrupts and lock the bus for exclusive

CPU use while they execute.

AM31

AM32

The BSET and BCLR instructions do not lock the bus for operations on data

in the cachable region of external memory.

Core icons

These indicate the applicable

microcontroller cores.

MN1030 Series

AM30: First generation

AM31: Second generation

MN103S Series

AM32: Third generation

Instruction Functions

7

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