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Chapter 1 Overview

2.6 Processor Status Word

PSW: Processor Status Word (16 bits x 1)

This 16-bit register displays CPU status and controls certain operations. Examples of the former function

include the flag bits indicating calculation results; of the latter, the interrupt mask level bits.

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0 0 S1 S0 IE IM2 IM1 IM0 0 0 0 0 V C N Z

Z: Zero flag

This bit goes to "1" if the calculation leaves "0" in all bits of the result and to "0" otherwise. After a reset, it

is "0."

N: Negative flag

This bit goes to "1" if the calculation leaves "1" in the most significant bit (MSB) of the result and to "0"

otherwise. After a reset, it is "0."

C: Carry flag

This bit goes to "1" if the calculation produces a carry out of or borrow into the most significant bit (MSB)

of the result and to "0" otherwise. After a reset, it is "0."

V: Overflow flag

This bit goes to "1" if the result exceeds the bounds for signed integers and to "0" otherwise. After a reset, it

is "0."

IM2 to IM0: Interrupt mask level

These three bits offer a choice of eight interrupt mask levels from 0 (000B) to 7 (111B). The hardware

accepts only interrupt requests with levels higher than the specified value, and, when it accepts one, sets

these bits to the interrupt request level to block subsequent interrupt requests at that and lower levels until

interrupt processing is complete. After a reset, all bits are "0" for an interrupt mask level of 0.

IE: Interrupt Enable

This control bit is normally "1" to enable interrupts. When the hardware accepts an interrupt request, however,

this bit goes to "0" to disable further interrupts. To support nested interrupts, the user application program

must, therefore, reset this bit to "1." After a reset, it is "0."

S1 to S0: Software Bits

These two bits are for operating system use in controlling software. They are not for use by user application

programs. After a reset, they are both "0."

Register Set

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