2026IVZ(2006) Ver la hoja de datos (PDF) - Intersil
Número de pieza
componentes Descripción
Fabricante
2026IVZ Datasheet PDF : 24 Pages
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ISL12026
AC Electrical Specifications (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS NOTES
tHD:STO STOP Condition Hold Time for
From SDA rising edge to SCL
600
Read, or Volatile Only Write
falling edge. Both crossing 70%
of VDD.
tDH
Output Data Hold Time
From SCL falling edge crossing
0
30% of VDD, until SDA enters the
30% to 70% of VDD window.
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip.
10
ns
ns
400
pF
Cpin SDA, and SCL Pin Capacitance
10
pF
tWC Non-volatile Write Cycle Time
12
20
ms
10
NOTES:
3. IRQ/FOUT Inactive.
4. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz
5. VDD > VBAT +VBATHYS
6. Bit BSW = 0 (Standard Mode), VBAT >= 1.8V
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
9. Parameter is not 100% tested.
10. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
Timing Diagrams
Bus Timing
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tF
tHIGH
tSU:DAT
tHD:STA
tLOW
tR
tHD:DAT
tAA
tDH
tHD:STO
tSU:STO
tBUF
Write Cycle Timing
SCL
SDA
8TH BIT OF LAST BYTE
ACK
tWC
STOP
CONDITION
START
CONDITION
5
FN8231.5
October 23, 2006
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