ISL12027 Ver la hoja de datos (PDF) - Intersil

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ISL12027

Real Time Clock/Calendar with EEPROM

Intersil 

ISL12027, ISL12027A

TABLE 4. DIGITAL TRIMMING REGISTERS

DTR REGISTER

DTR2

DTR1

DTR0

ESTIMATED FREQUENCY

PPM

0

0

0

0

0

1

0

+10

0

0

1

+20

0

1

1

+30

1

0

0

0

1

1

0

-10

1

0

1

-20

1

1

1

-30

PWR Register: SBIB, BSW, VTS2, VTS1, VTS0

SBIB: Serial Bus Interface (Enable)

The serial bus can be disabled in battery backup mode by

setting this bit to “1”. This will minimize power drain on the

battery. The Serial Interface can be enabled in battery

backup mode by setting this bit to “0” (default is “0”). See

“Power Control Operation” on page 15 and “RESET” on

page 9.

BSW: Power Control Bit

The Power Control bit, BSW, determines the conditions for

switching between VDD and Backup Battery. There are two

options:

Option 1. Standard: Set “BSW = 0” (default for ISL12027A)

Option 2. Legacy /Default Mode: Set “BSW = 1” (default

for ISL12027)

See “Power Control Operation” on page 15 for more details.

Also see “I2C Communications During Battery Backup and

LVR Operation” on page 24 for important details.

VTS2, VTS1, VTS0: VRESET Select Bits

The ISL12027 is shipped with a default VDD threshold

(VRESET) per the “Ordering Information” table on page 2.

This register is a non-volatile with no protection, therefore

any writes to this location can change the default value from

that marked on the package. If not changed with a non-

volatile write, this value will not change over normal

operating and storage conditions. However, ISL12027 has

four (4) additional selectable levels to fit the customers

application. Levels are: 4.64V (default), 4.38V, 3.09V, 2.92V

and 2.63V. The VRESET selection is via 3 bits (VTS2, VTS1

and VTS0). See Table 5.

Care should be taken when changing the VRESET select bits.

If the VRESET voltage selected is higher than VDD, then the

device will go into RESET and unless VDD is increased, the

device will no longer be able to communicate using the I2C

bus.

VTS2

0

0

0

0

1

VTS1

0

0

1

1

0

TABLE 5.

VTS0

0

1

0

1

0

VRESET

4.64V

4.38V

3.09V

2.92V

2.63V

In battery mode, the RESET signal output is asserted LOW

when the VDD voltage supply has dipped below the VRESET

threshold, but the RESET signal output will not return HIGH

until the device is back to VDD mode even the VDD voltage is

above VRESET threshold.

Device Operation

Writing to the Clock/Control Registers

Changing any of the bits of the clock/control registers

requires the following steps:

1. Write a 02h to the Status Register to set the Write Enable

Latch (WEL). This is a volatile operation, so there is no

delay after the write. (Operation preceded by a start and

ended with a stop).

2. Write a 06h to the Status Register to set both the Register

Write Enable Latch (RWEL) and the WEL bit. This is also

a volatile cycle. The zeros in the data byte are required.

(Operation proceeded by a start and ended with a stop).

Write all 8 bytes to the RTC registers, or one byte to the SR,

or one to five bytes to the control registers. This sequence

starts with a start bit, requires a slave byte of “11011110” and

an address within the CCR and is terminated by a stop bit. A

write to the EEPROM registers in the CCR will initiate a

non-volatile write cycle and will take up to 20ms to complete.

A write to the RTC registers (SRAM) will require much

shorter cycle time (t = tBUF). Writes to undefined areas have

no effect. The RWEL bit is reset by the completion of a write

to the CCR, so the sequence must be repeated to again

initiate another change to the CCR contents. If the sequence

is not completed for any reason (by sending an incorrect

number of bits or sending a start instead of a stop, for

example) the RWEL bit is not reset and the device remains

in an active mode. Writing all zeros to the status register

resets both the WEL and RWEL bits. A read operation

occurring between any of the previous operations will not

interrupt the register write operation.

Alarm Operation

Since the alarm works as a comparison between the alarm

registers and the RTC registers, it is ideal for notifying a host

processor of a particular time event and trigger some action as

a result. The host can be notified by polling the Status Register

(SR) Alarm bits. These two volatile bits (AL1 for Alarm 1 and

AL0 for Alarm 0), indicate if an alarm has happened. The AL1

and AL0 bits in the status register are reset by the falling edge

of the eighth clock of status register read.

14

FN8232.8

August 12, 2010

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