ISL12027 Ver la hoja de datos (PDF) - Intersil

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ISL12027

Real Time Clock/Calendar with EEPROM

Intersil 

ISL12027, ISL12027A

Alarm Registers (Non-Volatile)

Alarm0 and Alarm1

The alarm register bytes are set up identical to the RTC

register bytes, except that the MSB of each byte functions as

an enable bit (enable = “1”). These enable bits specify which

alarm registers (seconds, minutes, etc.) are used to make

the comparison. Note that there is no alarm byte for year.

The alarm function works as a comparison between the

alarm registers and the RTC registers. As the RTC

advances, the alarm will be triggered once a match occurs

between the alarm registers and the RTC registers. Any one

alarm register, multiple registers, or all registers can be

enabled for a match. See “Device Operation” on page 14

and “Application Section” on page 22 for more information.

Control Registers (Non-Volatile)

The Control Bits and Registers described in the following

section are non-volatile.

BL Register

BP2, BP1, BP0 - Block Protect Bits

The Block Protect Bits, BP2, BP1 and BP0, determine which

blocks of the array are write protected. A write to a protected

block of memory is ignored. The block protect bits will

prevent write operations to one of eight segments of the

array. The partitions are described in Table 3.

TABLE 3.

PROTECTED ADDRESSES

ISL12027

ARRAY LOCK

000

None (Default)

None

001

010

011

100

101

110

111

180h – 1FFh

100h – 1FFh

000h – 1FFh

000h – 03Fh

000h – 07Fh

000h – 0FFh

000h – 1FFh

Upper 1/4

Upper 1/2

Full Array

First 4 Pages

First 8 Pages

First 16 Pages

Full Array

Oscillator Compensation Registers

There are two trimming options.

• ATR. Analog Trimming Register

• DTR. Digital Trimming Register

These registers are non-volatile. The combination of analog

and digital trimming can give up to -64 to +110ppm of total

adjustment.

ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,

ATR0: Analog Trimming Register

Six analog trimming bits, ATR0 to ATR5, are provided in

order to adjust the on-chip load capacitance value for

frequency compensation of the RTC. Each bit has a different

weight for capacitance adjustment. For example, using a

Citizen CFS-206 crystal with different ATR bit combinations

provides an estimated ppm adjustment range from -34ppm

to +80ppm to the nominal frequency compensation.

X1

CX1

X2

CX2

CRYSTAL

OSCILLATOR

FIGURE 12. DIAGRAM OF ATR

The effective on-chip series load capacitance, CLOAD,

ranges from 4.5pF to 20.25pF with a mid-scale value of

12.5pF (default). CLOAD is changed via two digitally

controlled capacitors, CX1 and CX2, connected from the X1

and X2 pins to ground (see Figure 12). The value of CX1 and

CX2 is given Equation 1:

CX = (16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9)pF

(EQ. 1)

The effective series load capacitance is the combination of

CX1 and CX2:

CLOAD

=

----------------1------------------

⎛

⎝

-----1-----

CX1

+

C-----1X----2-⎠⎞

(EQ. 2)

CLOAD

=

⎛

⎝

-1--6-----⋅---b---5----+-----8----⋅---b---4-----+----4----⋅---b----3----+----2-2----⋅---b---2----+----1-----⋅---b---1----+-----0---.-5----⋅----b---0----+----9--⎠⎞

p

F

For example, CLOAD(ATR = 00000) = 12.5pF,

CLOAD(ATR = 100000) = 4.5pF, and

CLOAD(ATR = 011111) = 20.25pF. The entire range for the

series combination of load capacitance goes from 4.5pF to

20.25pF in 0.25pF steps. Note that these are typical values.

DTR Register - DTR2, DTR1, DTR0: Digital

Trimming Register

The digital trimming Bits DTR2, DTR1 and DTR0 adjust the

number of counts per second and average the ppm error to

achieve better accuracy.

DTR2 is a sign bit. DTR2 = 0 means frequency

compensation is >0. DTR2 = 1 means frequency

compensation is <0.

DTR1 and DTR0 are scale bits. DTR1 gives 10ppm

adjustment and DTR0 gives 20ppm adjustment.

A range from -30ppm to +30ppm can be represented by

using the three DTR bits.

13

FN8232.8

August 12, 2010

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