FAN7530 Ver la hoja de datos (PDF) - Fairchild Semiconductor
Número de pieza
componentes Descripción
Fabricante
FAN7530 Datasheet PDF : 20 Pages
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Pin Assignments
VCC
OUT
GND
ZCD
8
7
6
5
YWW
FAN7530
1
2
3
4
INV
MOT
COMP
CS
FAN7530 Rev. 00
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
1
INV
2
MOT
3
COMP
4
CS
5
ZCD
6
GND
7
OUT
8
VCC
Description
This pin is the inverting input of the error amplifier. The output voltage of the boost PFC
converter should be resistively divided to 2.5V.
This pin is used to set the slope of the internal ramp. The voltage of this pin is main-
tained at 3V. If a resistor is connected between this pin and GND, current flows out of
the pin and the slope of the internal ramp is proportional to this current.
This pin is the output of the transconductance error amplifier. Components for the out-
put voltage compensation should be connected between this pin and GND.
This pin is the input of the over-current protection comparator. The MOSFET current is
sensed using a sensing resistor and the resulting voltage is applied to this pin. An
internal RC filter is included to filter switching noise.
This pin is the input of the zero current detection block. If the voltage of this pin goes
higher than 1.5V, then goes lower than 1.4V, the MOSFET is turned on.
This pin is used for the ground potential of all the pins. For proper operation, the signal
ground and the power ground should be separated.
This pin is the gate drive output. The peak sourcing and sinking current levels are
+500mA and -800mA respectively. For proper operation, the stray inductance in the
gate driving path must be minimized.
This pin is the IC supply pin. IC current and MOSFET drive current are supplied using
this pin.
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.2
3
www.fairchildsemi.com
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