ADM1066(Rev0) Ver la hoja de datos (PDF) - Analog Devices
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ADM1066 Datasheet PDF : 32 Pages
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ADM1066
Parameter
Min
Conversion Time
Offset Error
Input Noise
BUFFERED VOLTAGE OUTPUT DACs
Resolution
Code 0x80 Output Voltage
Range 1
Range 2
Range 3
Range 4
Output Voltage Range
LSB Step Size
INL
DNL
Gain Error
Load Regulation
0.592
0.796
0.996
1.246
Maximum Load Capacitance
Settling Time into 50 pF Load
Load Regulation
PSRR
REFERENCE OUTPUT
Reference Output Voltage
Load Regulation
2.043
Minimum Load Capacitance
1
Load Regulation
PSRR
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode (PDO1–6)
Output Impedance
VOH
11
10.5
IOUTAVG
Standard (Digital Output) Mode (PDO1–10)
VOH
2.4
VOL
IOL2
ISINK2
RPULL-UP
ISOURCE (VPn)2
VPU − 0.3
0
Three-State Output Leakage Current
Oscillator Frequency
90
Typ Max
0.44
84
±2
0.25
8
0.6
0.8
1
1.25
601.25
2.36
-4
2
2.5
60
40
0.603
0.803
1.003
1.253
±0.75
±0.4
1
50
2
2.048
−0.25
0.25
2.053
2
60
500
12.5 14
12
13.5
20
4.5
0.50
20
60
20
2
10
100 110
Unit
ms
ms
LSB
LSBrms
Test Conditions/Comments
One conversion on one channel
All 12 channels selected, 16x averaging enabled
VREFIN = 2.048 V
Direct input (no attenuator)
Bits
6 DACs are individually selectable for centering on
one of four output voltage ranges
V
V
V
V
mV Same range, independent of center point
mV
LSB Endpoint corrected
LSB
%
mV
Sourcing Current, IREFOUTMA X= -200µA
mV
Sinking Current, IREFOUTMA X= 100µA
pF
µs
mV Per mA
dB
DC
dB
100 mV step in 20 ns with 50 pF load
V
No load
mV
Sourcing current, IDACnMAX = −100 µA
mV
Sinking current, IDACnMAX = 100 µA
µF
Capacitor required for decoupling, stability
mV Per 100 µA
dB
DC
kΩ
V
IOH = 0
V
IOH = 1µA
µA
2 V < VOH < 7 V
V
VPU (pull-up to VDDCAP or VPN) = 2.7 V, IOH = 0.5 mA
V
VPU to Vpn = 6.0 V, IOH = 0 mA
V
VPU ≤ 2.7 V, IOH = 0.5 mA
V
IOL = 20 mA
mA Maximum sink current per PDO pin
mA Maximum total sink for all PDOs
kΩ
Internal pull-up
mA Current load on any VPn pull-ups, that is, total
source current available through any number of
PDO pull-up switches configured onto any one
µA
VPDO = 14.4 V
kHz All on-chip time delays derived from this clock
Rev. 0 | Page 5 of 32
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