ADM1066(Rev0) Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
ADM1066 Datasheet PDF : 32 Pages
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GENERAL DESCRIPTION
(continued from Page 1)
Supply margining can be performed with a minimum of
external components. The margining loop can be used for in-
circuit testing of a board during production (for example, to
verify the board’s functionality at −5% of nominal supplies),
or can be used dynamically to accurately control the output
voltage of a dc/dc converter.
The device also provides up to ten programmable inputs for
monitoring under, over, or out-of-window faults on up to ten
supplies. In addition, ten programmable outputs can be used as
logic enables. Six of them can also provide up to a 12 V output
for driving the gate of an N-channel FET, which can be placed
in the path of a supply.
ADM1066
The logical core of the device is a sequencing engine. This state-
machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs,
based on the condition of the inputs.
The device is controlled via configuration data that can be
programmed into an EEPROM. The whole configuration can
be programmed using an intuitive GUI-based software package
provided by ADI.
AUX2 AUX1
REFIN REFOUT REFGND SDA SCL A1 A0
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
VH
SFDGND
VDDCAP
SELECTABLE
ATTENUATOR
SELECTABLE
ATTENUATOR
VDD
ARBITRATOR
ADM1066
VREF
SMBus
INTERFACE
12-BIT
SAR ADC
DEVICE
CONTROLLER
OSC
EEPROM
GPI SIGNAL
CONDITIONING
SFD
CONFIGURABLE
O/P DRIVER
(HV)
GPI SIGNAL
CONDITIONING
SFD
SFD
SEQUENCING
ENGINE
CONFIGURABLE
O/P DRIVER
(HV)
CONFIGURABLE
O/P DRIVER
(LV)
SFD
REG 5.25V
CHARGE PUMP
VOUT
DAC
CONFIGURABLE
O/P DRIVER
(LV)
VOUT
DAC
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
PDOGND
GND
VCCP
DAC1 DAC2 DAC3 DAC4 DAC5 DAC6
Figure 2. Detailed Block Diagram
Rev. 0 | Page 3 of 32
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