RTL8111E Ver la hoja de datos (PDF) - Realtek Semiconductor

Número de pieza

componentes Descripción

Fabricante

RTL8111E

INTEGRATED GIGABIT ETHERNET CONTROLLER FOR PCI EXPRESS APPLICATIONS

Realtek Semiconductor 

5. Pin Descriptions

The signal type codes below are used in the following tables:

I: Input

S/T/S: Sustained Tri-State

O: Output

O/D: Open Drain

T/S: Tri-State bi-directional input/output pin

P: Power

RTL8111E

Datasheet

5.1. Power Management/Isolation

Symbol

LANWAKEB

ISOLATEB

Type

O/D

I

Table 1. Power Management/Isolation

Pin No Description

Power Management Event: Open drain, active low.

28 Used to reactivate the PCI Express slot’s main power rails and reference clocks.

Refer to the reference schematic for strapping pin information.

All strapping pins are power-on-latch pins.

Isolate Pin: Active low.

26

Used to isolate the RTL8111E from the PCI Express bus. The RTL8111E will not

drive its PCI Express outputs (excluding LANWAKEB) and will not sample its

PCI Express input as long as the Isolate pin is asserted.

5.2. PCI Express Interface

Symbol

REFCLK_P

REFCLK_N

HSOP

HSON

HSIP

HSIN

PERSTB

CLKREQB

Type

I

I

O

O

I

I

I

O/D

Pin No

19

20

22

23

17

18

25

16

Table 2. PCI Express Interface

Description

PCI Express Differential Reference Clock Source: 100MHz ± 300ppm.

PCI Express Transmit Differential Pair.

PCI Express Receive Differential Pair.

PCI Express Reset Signal: Active low.

When the PERSTB is asserted at power-on state, the RTL8111E returns to a

pre-defined reset state and is ready for initialization and configuration after the

de-assertion of the PERSTB.

Reference Clock Request Signal.

This signal is used by the RTL8111E to request starting of the PCI Express

reference clock.

Refer to the reference schematic for strapping pin information.

All strapping pins are power-on-latch pins.

Integrated Gigabit Ethernet Controller for PCI Express

5

Track ID: JATR-2265-11 Rev. 1.5

Share Link: