LBFS Ver la hoja de datos (PDF) - Linear Technology

Número de pieza

componentes Descripción

Fabricante

LBFS

16-/14-/12-Bit Rail-to-Rail DACs in 10-Lead DFN

Linear Technology 

LTC2601/LTC2611/LTC2621

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2601/LTC2611/LTC2621

Short-Circuit Output Current vs

VOUT (Sinking)

50

VCC = 5.5V

VREF = 5.6V

40 CODE = 0

VOUT SWEPT 0V TO VCC

Short-Circuit Output Current vs

VOUT (Sourcing)

0

VCC = 5.5V

VREF = 5.6V

–10 CODE = FULL SCALE

VOUT SWEPT VCC TO 0V

30

–20

20

–30

10

0

012

3

4

5

6

1V/DIV

2601 G15

–40

–50

0

1

2

3

4

5

6

1V/DIV

2601 G16

PIN FUNCTIONS

SDO (Pin 1): Serial Interface Data Output. This pin is used

for daisy-chain operation. The serial output of the shift

register appears at the SDO pin. The data transferred to

the device via the SDI pin is delayed 32 SCK rising edges

before being output at the next falling edge. SDO is an

active output and does not go high impedance even when

CS/LD is taken to a logic high level.

SDI (Pin 2): Serial Interface Data Input. Data is applied

to SDI for transfer to the device at the rising edge of SCK

(Pin 3). The LTC2601 accepts input word lengths of either

24 or 32 bits.

SCK (Pin 3): Serial Interface Clock Input. CMOS and TTL

compatible.

CLR (Pin 4): Asynchronous Clear Input. A logic low at this

level-triggered input clears all registers and causes the

DAC voltage outputs to drop to 0V for LTC2601/LTC2611/

LTC2621. A logic low at this input sets all registers to

midscale code and causes the DAC voltage outputs to go

to midscale for LTC2601-1/LTC2611-1/LTC2621-1. CMOS

and TTL compatible.

CS/LD (Pin 5): Serial Interface Chip Select/Load Input.

When CS/LD is low, SCK is enabled for shifting data on

SDI into the register. When CS/LD is taken high, SCK

is disabled and the specified command (see Table 1) is

executed.

REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC.

VOUT (Pin 7): DAC Analog Voltage Output. The output

range is 0V to VREF.

GND (Pin 8): Analog Ground.

VCC (Pin 9): Supply Voltage Input. 2.5V ≤ VCC ≤ 5.5V.

LDAC (Pin 10): Asynchronous DAC Update Pin. If CS/LD

is high, a falling edge on LDAC immediately updates the

DAC register with the contents of the input register (similar

to a software update). If CS/LD is low when LDAC goes

low, the DAC register is updated after CS/LD returns high.

A low on the LDAC pin powers up the DAC. A software

power down command is ignored if LDAC is low.

Exposed Pad (Pin 11): Ground. Must be soldered to PCB

ground.

2601fb

9

Share Link: