WS57C256F-70J Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

Fabricante

WS57C256F-70J

HIGH SPEED 32K x 8 CMOS EPROM

STMicroelectronics 

AC READ TIMING DIAGRAM

ADDRESSES

CE

OE

OUTPUTS

VALID

tACC

tOH

tCE

tOE

tDF

VALID

tDF

WS57C256F

CAPACITANCE(5) TA = 25°C, f = 1 MHz

SYMBOL

PARAMETER

CONDITIONS

CIN

COUT

CVPP

Input Capacitance

Output Capacitance

VPP Capacitance

VIN = 0V

VOUT = 0V

VPP = 0 V

NOTES: 5. This parameter is only sampled and is not 100% tested.

6. Typical values are for TA = 25°C and nominal supply voltages.

TYP (6)

4

8

18

MAX

6

12

25

UNITS

pF

pF

pF

TEST LOAD (High Impedance Test Systems)

A.C. TESTING INPUT/OUTPUT WAVEFORM

2.01 V

D.U.T.

98 Ω

30 pF

(INCLUDING SCOPE

AND JIG

CAPACITANCE)

3.0

2.0

2.0

TEST

POINTS

0.0

0.8

0.8

A.C. testing inputs are driven at 3.0 V for a logic "1" and 0.0 V

for a logic "0." Timing measurements are made at 2.0 V for a

logic "1" and 0.8 V for a logic "0".

NOTE: 7. Provide adequate decoupling capacitance as close as possible to this device to achieve the published A.C. and D.C. parameters.

A 0.1 microfarad capacitor in parallel with a 0.01 microfarad capacitor connected between VCC and ground is recommended.

Inadequate decoupling may result in access time degradation or other transient performance failures.

3-15

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