SPT561 Ver la hoja de datos (PDF) - Signal Processing Technologies

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SPT561

WIDEBAND, LOW DISTORTION DRIVER AMPLIFIER

Signal Processing Technologies 

For the circuit of Figure 1, the equivalent input noise

voltage may be calculated using the data sheet spot

noises and Rs = 25Ω, RL = ∞. Recall that 4kT = 16E-21J. All

terms cast as (nV/√Hz)2

en = (2.1)2 + (.07)2 + (.632)2 + (1.22)2 + (.759)2 + (.089)2

= 2.62nV/ Hz

Gain Accuracy (DC):

A classical op amp’s gain accuracy is principally set by the

accuracy of the external resistors. The SPT561 also de-

pends on the internal characteristics of the forward current

gain and inverting input impedance. The performance equa-

tions for Av and Ro along with the Thevinin model of Figure 5

are the most direct way of assessing the absolute gain

accuracy. Note that internal temperature drifts will decrease

the absolute gain slightly as the part warms up. Also note

that the parameter tolerances affect both the signal gain and

output impedance. The gain tolerance to the load must

include both of these effects as well as any variation in the

load. The impact of each parameter shown in the perfor-

mance equations on the gain to the load (AL) is shown

below.

Increasing current gain G

Increasing inverting input Ri

Increasing Rf

Increasing Rg

Increases AL

Decreases AL

lncreases AL

Decreases AL

Applications Suggestions

Driving a Capacitive Load:

The SPT561 is particularly suitable for driving a capacitive

load. Unlike a classical op amp (with an inductive output

impedance), the SPT561’s output impedance, while starting

out real at the programmed value, goes somewhat capaci-

tive at higher frequencies. This yields a very stable perfor-

mance driving a capacitive load. The overall response is

limited by the (1/RC) bandwidth set by the SPT561’s output

impedance and the load capacitance. It is therefore advan-

tageous to set a low Ro with the constraint that extremely

low Rf values will degrade the distortion performance. Ro =

25Ω was selected for the data sheet plots. Note from

distortion plots into a capacitive load that the SPT561

achieves better than 60dBc THD (10-bits) driving 2Vpp into a

50pF load through 30MHz.

Improving the Output Impedance Match

vs. Frequency - Using Rx:

Using the loop gain to provide a non-zero output impedance

provides a very good impedance match at low frequencies.

As shown on the Output Return Loss plot, however, this

match degrades at higher frequencies. Adding a small

external resistor in series with the output, Rx, as part of the

output impedance (and adjusting the programmed Ro ac-

cordingly) provides a much better match over frequency.

Figure 9 shows this approach.

Vi

Rs

+

Cx

SPT561

-

Rf

Rg

R'o = Rx + Ro

Rx

Vo

RL Ro = R'o - Rx

With:

Ro = SPT561 output impedance

and Ro + Rx = RL generally

Figure 9: Improving Output Impedance

Match vs. Frequency

Increasing Rx will decrease the achievable voltage swing at

the load. A minimum Rx should be used consistent with the

desired output match. As discussed in the thermal analysis

discussion, Rx is also very useful in limiting the internal

power under an output shorted condition.

Interpreting the Slew Rate:

The slew rate shown in the data sheet applies to the voltage

swing at the load for the circuit of Figure 1. Twice this value

would be required of a low output impedance amplifier using

an external matching resistor to achieve the same slew rate

at the load.

Layout Suggestions:

The fastest fine scale pulse response settling requires

careful attention to the power supply decoupling. Generally,

the larger electrolytic capacitor ground connections should

be as near the load ground (or cable shield connection) as is

reasonable, while the higher frequency ceramic de-coupling

caps should be as near the SPT561’s supply pins as

possible to a low inductance ground plane.

Evaluation Boards:

An evaluation board (showing a good high frequency layout)

for the SPT561 is available. This board may be ordered as

part #730019.

Thermal Analysis and Protection

A thermal analysis of a chip and wire hybrid is directed at

determining the maximum junction temperature of all the

internal transistors. From the total internal power dissipa-

tion, a case temperature may be developed using the

ambient temperature and the case to ambient thermal

impedance. Then, each of the dominant power dissipating

paths are considered to determine which has the maximum

rise above case temperature.

The thermal model and analysis steps are shown below. As

is typical, the model is cast as an electrical model where the

temperatures are voltages, the power dissipators are cur-

rent sources, and the thermal impedances are resistances.

Refer to the summary design equations and Figure 1 for a

description of terms.

SPT561

11

10/9/98

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