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ADP3154

5-Bit Programmable Dual Power Supply Controller for Pentium® III Processors

Analog Devices 

ADP3154

of a resistor and capacitor. The required resistor value can be

calculated from the equation:

where

RC = 275 kΩ × RtTOTAL

275 kΩ – RtTOTAL

RtTOTAL = 16.4 kΩ × RCS × IOMAX

VHI – VLO

and where the quantities 16.4 kΩ and 275 kΩ are characteristics

of the ADP3154 and the value of the current sense resistor, RCS,

has already been determined as above.

Although a single termination resistor equal to RC would yield

the proper voltage positioning gain, the dc biasing of that resis-

tor would determine how the regulation band is centered (i.e.,

offset). Note that sometimes the specified regulation band is

asymmetrical with respect to the nominal VID voltage. With the

ADP3154, the offset is already considered part of the design

procedure—no special provision is required. To accomplish the

dc biasing, it is simplest to use two resistors to terminate the gm

amplifier output, with the lower resistor tied to ground and the

upper resistor to the 12 V supply of the IC. The values of these

resistors can be calculated using:

RUPPER

=

RC

×VDIV

VOS

and

RLOWER = RC ×

VOS

VDIV – VOS

where VDIV is the resistor divider supply voltage (e.g., the rec-

ommended 12 V), and VOS is the offset voltage required on the

amplifier to produce the desired offset at the output. VOS is

calculated using Equation 2 below, where VOUT(OS) is the offset

from the nominal VID-programmed value to the center of the

specified regulation window for the output voltage. (Note this

may be either positive or negative.) For clarification, that offset

is given by:

VOUT(OS)

=

1

2 (VHI

+VLO

)

–VID

where VHI and VLO are the respective upper and lower limits

allowed for regulation.

Finally, the compensating capacitance is determined from the

equality of the pole frequency of the error amplifier gain and the

zero frequency of the impedance of the output capacitor:

CCOMP

=

CO × ESR

RtTOTAL

Trade-Offs Between DC Load Regulation and AC Load

Regulation

Casual observation of the circuit operation—e.g., with a voltmeter

—would make it appear that the dc load regulation appears

to be rather poor compared to a conventional regulator. This

would be especially noticeable under very light or very heavy

loads where the voltage is “positioned” near one of the extremes

of the regulation window rather than near the nominal center

value. It must be noted and understood that this low gain char-

acteristic (i.e., loose dc load regulation) is inherently required to

allow improved transient containment (i.e., to achieve tighter ac

load regulation). That is, the dc load regulation is intentionally

sacrificed (but kept within specification) in order to minimize

the number of capacitors required to contain the load transients

produced by the CPU.

Linear Regulator

The ADP3154 linear regulator provides a low cost, convenient

and versatile solution for generating additional lower supply rails

that can be programmed in the range 1.2 V–5 V. The maximum

output load current is determined by the size and thermal

impedance of the external N-channel power MOSFET that is

placed in series with the supply and controlled by the ADP3154.

The output voltage, VOLDO1 in Figure 14, is sensed at the FB

pin of the ADP3154 and compared to an internal 1.2 V refer-

ence in a negative feedback loop which keeps the output voltage

in regulation. If the load is being reduced or increased, the FET

drive will also be reduced or increased by the ADP3154 to pro-

vide a well regulated ± 1% accurate output voltage. The output

voltage is programmed by adjusting the value of the external

resistor RPROG, shown in Figure 14.

VO2 = 3.3V

IO2 = 0.5A

VIN = +5V

RS2

1.1⍀

IRLR2703

ADP3154

2k⍀

VLDO

470pF

2N2222

FB

1000␮F/10V

RPROG

35k ⍀

20k ⍀

Figure 14. Linear Regulator with Overcurrent Protection

Efficiency of the Linear Regulator

The efficiency and corresponding power dissipation of the linear

regulator are not determined by the ADP3154. Rather, these

are a function of input and output voltage and load current.

Efficiency is approximated by the formula:

η = 100% × (VOUT Ϭ VIN)

The corresponding power dissipation in the MOSFET, together

with any resistance added in series from input to output is given

by:

PLDO = (VIN(LDO) – VOUT(LDO)) × IOUT(LDO)

Minimum power dissipation and maximum efficiency are ac-

complished by choosing the lowest available input voltage that

exceeds the desired output voltage. However, if the chosen

input source is itself generated by a linear regulator, its power

dissipation will be increased in proportion to the additional

current it must now provide. For most PC systems, the lowest

available input source for the linear regulators which is not itself

generated by a linear regulator is 3.3 V from the main power

supply.

VOS

=

RC

RtTOTAL



× 0.8 V



+



VOUT (OS)

RtTOTAL





1.36 kΩ

– 1.7 V

 RtTOTAL 





 275 kΩ 

+6



RCS

IOMAX





(2)

–10–

REV. A

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