ADP3157 Ver la hoja de datos (PDF) - Analog Devices
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ADP3157 Datasheet PDF : 12 Pages
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ADP3157
The maximum rms current of the low side FET is:
IRMSLS = [DMAXLF (ILVALLEY2 + ILPEAK2 + ILVALLEYILPEAK)/3]0.5
= 12.5 A rms
The RDS(ON) for each FET can be derived from the allowable
dissipation. If 5% of the maximum output power is allowed for
FET dissipation, the total dissipation will be:
PFETALL = 0.05 VOIOMAX = 1.7 W
Allocating half of the total dissipation for the high side FET and
half for the low side FET, the required minimum FET resis-
tances will be:
RDS(ON)HSF(MIN) = 0.85 W/(11.6 A)2 = 6 mΩ
RDS(ON)LSF(MIN) = 0.85 W/(12.5 A)2 = 5.5 mΩ
Note that there is a trade-off between converter efficiency and
cost. Larger FETs reduce the conduction losses and allow
higher efficiency, but increase the system cost. If efficiency is
not a major concern, the International Rectifier IRL3803 is an
economical choice for both the high side and low side positions.
Those devices have an RDS(ON) of 6 mΩ at VGS = 10 V and at
+25°C. The low side FET is turned on with at least 10 V. The
high side FET, however, is turned on with only 12 V – 5 V = 7 V.
The specified RDS(ON) at the expected highest FET junction
temperature of +140°C must be modified by:
RDS(ON)MULT = 1.7
Using this multiplier, the expected RDS(ON) at +140°C is 1.7 ×
6 mΩ = 10 mΩ.
The high side FET dissipation is:
PDFETHS = IRMSHS2RDS(ON) + 0.5 VINILPEAKQGfMIN/IG ~ 2.3 W
where the second term represents the turn-off loss of the FET.
(In the second term, QGS is the gate charge to be removed from
the gate for turn-off and IG is the gate current. From the data
sheet, QGS is a 41 nC and the peak gate drive current provided
by the ADP3157 is about 1 A.)
The low side FET dissipation is:
PDFETLS = IRMSLS2RDS(ON) = 1.6 W
(Note that there are no switching losses in the low side FET.)
To maintain an acceptable MOSFET junction temperature,
proper heat sinks should be used. The Thermalloy 6030 heat
sink has a thermal impedance of 13°C/W with convection cool-
ing. With this heat sink, the junction-to-ambient thermal imped-
ance of the chosen high side FET θJAHS will be 13°C/W (heat
sink-to-ambient) + 2°C/W (junction-to-case) + 0.5°C/W (case-
to-heat sink) = 15.5°C/W.
At full load, and at +50°C ambient temperature, the junction
temperature of the high side FET is:
TJHSMAX = TA + θJAHS PDFETHS = +86°C
The same heat sink may be used for the low side FET, e.g., the
Thermalloy type 7141 (θ = 20.3°C/W). With this heat sink, the
junction temperature of the low side FET is:
TJLSMAX = TA + θJALS PDFETLS = +82.5°C
All of the above-calculated junction temperatures are safely
below the +175°C maximum specified junction temperature of
the selected FETs.
The maximum operating junction temperature of the ADP3157
is calculated as follows:
TJICMAX = TA + θJA (IICVCC + PDR)
where θJA is the junction-to-ambient thermal impedance of the
ADP3157 and PDR is the drive power. From the data sheet, θJA
is equal to 110°C/W and IIC = 2.7 mA. PDR can be calculated as
follows:
PDR = (CRSS + CISS)VCC2 fMAX = 307 mW
The result is:
TJICMAX = +86°C
CIN Selection and Input Current di/dt Reduction
In continuous inductor-current mode, the source current of the
high side MOSFET is a square wave with a duty ratio of VOUT/
VlN. To keep the input ripple voltage at a low value, one or more
capacitors with low equivalent series resistance (ESR) and ad-
equate ripple-current rating must be connected across the input
terminals. The maximum rms current of the input bypass ca-
pacitors is:
ICINRMS = 0.5 IOMAX = 8.5 A rms
For an FA-type capacitor with 2700 µF capacitance and
10 V voltage rating, the ESR is 34 mΩ and the allowed ripple
current at 100 kHz is 1.94 A. At +105°C, at least four such
capacitors must be connected in parallel to handle the calculated
ripple current. At +50°C ambient, however, a higher ripple
current can be tolerated, so three capacitors in parallel are
adequate.
The ripple voltage across the three paralleled capacitors is:
VCINRPL = IOMAX [ESRIN/3 +DMAXHF/(3 CIN fMIN )] =
100 mV p-p
To further reduce the effect of the ripple voltage on the system
supply voltage bus and to reduce the input-current di/dt to
below the recommended maximum of 0.1 A/µs, an additional
small inductor (L > 1.7 µH @ 10 A) should be inserted between
the converter and the supply bus (see Figure 2).
Feedback Loop Compensation Design for Active Voltage
Positioning
Optimized compensation of the ADP3157 allows the best pos-
sible containment of the peak-to-peak output voltage deviation.
Any practical switching power converter is inherently limited by
the inductor in its output current slew rate to a value much less
than the slew rate of the load. Therefore, any sudden change of
load current will initially flow through the output capacitors,
and this will produce an output voltage deviation equal to the
ESR of the output capacitor array times the load current change.
REV. A
–9–
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