AD7304BN Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD7304BN Datasheet PDF : 14 Pages
| |||
AD7304/AD7305
SDI
SA SI A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
CLK
CS
tCSS
LDAC
tLD1
tCSH
tLD2
SDI
CLK
LDAC
CLR
FS
VOUT
ZS
tDS
tCL
tDH
tCH
tLDW
tCLRW
tS
؎1 LSB
ERROR BAND
tS
Figure 2. AD7304 Timing Diagram
SDI/SHDN
tSDN
tSDR
IDD
Figure 3. AD7304 Timing Diagram
Table I. AD7304 Control Logic Truth Table
CS CLK LDAC CLR Serial Shift Register Function Input REG Function
DAC Register Function
HXH
L
↑+ H
↑+ L
H
HXL
HXH
HXH
H
No Effect
H
Data Advanced 1 Bit
H
No Effect
H
No Effect
↓–
No Effect
↑+ No Effect
No Effect
No Effect
Updated with SR Contents2
Latched with SR Contents2
Loaded with 00H
Latched with 00H
No Effect
No Effect
No Effect
All Input Register Contents Transferred3
Loaded with 00H
Latched with 00H
NOTES
1↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.
2One Input Register receives the data bits D7–D0 decoded from the SR address bits (A1, A0); where REG A = (0, 0); B = (0, 1); C = (1, 0); D = (1, 1).
3LDAC is a level-sensitive input.
Table II. AD7304 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
LSB
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
AD7304 SAC SDC A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
If B11 (SAC), Shutdown All Channels, is set to logic LOW, all DACs are placed in a power shutdown mode, all output voltages become high resistance. If B10 (SDC),
Shutdown Decoded Channel, is set to logic LOW, only the DAC decoded by address bits A1 and A0 is placed in the shutdown mode.
–4–
REV. A
Share Link: 