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SA9401

UNIVERSAL PABX TONE GENERATOR

South African Micro Electronic Systems 

SA9401

FUNCTIONAL DESCRIPTION

The design of the SA9401 has been based on the assumption that any supervisory tone

used in a PABX (e.g. Dial tone or Busy Tone etc) can be described by a small set of

simple parameters and that the tones will be injected into a standard PCM 30 (2048kHz)

backplane in either A-law or µ-law format.

In the SA9401 a tone is created by repeating a fundamental waveform (or one of two

waveforms) which would typically be one cycle of a sinewave or alternatively may be

several cycles of a higher frequency signal (say 400 to 1000Hz) modulated by a lower

frequency signal. This Tone may then be interrupted (“Cadenced”) so that the tone is

effectively switched on and off.

The waveform shape, number of samples per cycle and the cadence can all be set by

the system designer in accordance with the related National Standards.

Once a set of tones have been described they may then be injected into the PCM

backplane. The time slot associated with each tone can be set by the system designer.

The SA9401 accommodates up to 9 different Tones to form a Tone Plan making ample

allowance for Ring, Dial, Busy, Intrude and other Tones. The set of data describing one

Tone Plan (waveforms, cadence timings, timeslots etc) is referred to as a Program and

is stored in an external EPROM which is addressed directly by the SA9401.

Up to eight Tone Plans may be stored and selected at will to accommodate products for

multi-national markets.

ARCHITECTURE

The architecture of the SA9401 consists of 6 functional blocks each of which is de-

scribed in detail in the following sections. Refer also to the block diagram.

Clock Generator

The clock generator circuit derives all the timing for the ic from either a 2048kHz or a

8192kHz clock. The desired Clock is selected by the state of the CLK_SEL pin (1 for

2048kHz and 0 for 8192kHz).

The CLK_SEL pin also determines the function of the Frame Sync pin. If CLK_SEL is

low then Internal synchronisation is assumed and FS1 should be tied high. If CLK_SEL

is high then an external Frame Synchronisation source must be connected to /FS1.

The Clock Generator comprises 5 functional blocks.

A divide-by-4 counter is enabled only if a 8192kHz clock is selected so that all internal

timing is based on 2048kHz. The Time Slot Counter keeps track of the Time Slots (0

to 31) in the PCM Frame while the bit position (0 to 7) in each time-slot is tracked by the

Bit Position Counter. PCM frame synchronisation signals are controlled by the Frame

Generator. Long cadence intervals are accommodated by the Five-ms-Timebase

which delivers a 200Hz signal which clocks the Cadence Timers.

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