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A16450

Universal Asynchronous Receiver/Transmitter

Altera Corporation 

a16450 Universal Asynchronous Receiver/Transmitter Data Sheet

Receiver Buffer Register

The receiver buffer register is a read-only register that contains the last

complete data word sample received by the a16450.

Transmitter Holding Register

The transmitter holding register is a write-only register that loads the next

data byte to be transmitted by the a16450.

Divisor Register

The divisor register controls the programmable baud rate generator. The

16-bit divisor performs an integer frequency divide of the input clock. The

nbaudout output becomes the transmitter clock that operates at 16 times

the baud rate clock. For example, if the input clock is 10 MHz and the

divisor register is set to a binary 2 (0000000000000010), the nbaudout

will be a 5-MHz output with a 50/50 duty cycle. The effective baud rate

will be 1/16th of 5 MHz, or 312,500 baud. In addition, the nbaudout

output may be wrapped to the receiver section input clock (rclk) to

provide the receiver clock that operates at 16 times the baud rate clock.

The a16450 does not support a divide-by-0 operation, which produces

the same results as a divide-by-1 operation for the nbaudout output.

However, a divide-by-0 operation prevents the transmitter from

functioning because an internal signal, baud_en, is not generated. The

baud_en signal enables the clock in the transmitter.

Interrupt Enable Register

The a16450 supports interrupts from four different sources; the interrupt

enable register selectively enables or disables interrupts from each of

these sources. When a bit is reset to a logic low, the a16450 will not

recognize interrupts from that source. Table 3 shows the interrupt enable

register format.

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Altera Corporation

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