ST70137 Ver la hoja de datos (PDF) - STMicroelectronics
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ST70137 Datasheet PDF : 22 Pages
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ST70137
PIN DESCRIPTION (continued)
Signal Name Direction Init Status Polarity
Signal Description
CFG_MEM INTERFACE
CFG_SCE
O
L
H
Chip Enable
This pin is designed to directly interface to a serial
EEPROM that use the 93C66 EEPROM interface proto-
col. This pin has to be connected directly to the
EEPROM’s chip select pin.
CFG_SCK/GPO[ 6]
O
L
-
Serial Clock or General Purpose Output Pin 6 depending
on the internal selection. The selection is performed writ-
ing the proper bit inside the PCFW or UCFW register. At
the power-on or hardware reset the CFG_CLK functional-
ity is selected. This pin is designed to directly interface to
a serial EEPROM that use the 93C66 EEPROM interface
protocol.
CFG_SDI
I
I
H
Serial Data Input
Data going into this pin has to be generated on the rising
edge of CFG_SCK. This pin is designed to directly inter-
face to a serial EEPROM that use the 93C66 EEPROM
interface protocol.
CFG_SDO/GPO[ 7]
O
L
-
Serial Data/Address Output
General Purpose Output Pin 7 depending on the internal
selection. The selection is performed writing the proper bit
inside the PCFW or UCFW register. At the power-up or
hardware reset the CFG_SDO functionality is selected.
The CFG_SDO data change is synchronous with the fall-
ing edge of CFG_SCK. This pin is designed to directly
interface to a serial EEPROM that use the 93C66
EEPROM interface protocol.
JTAG INTERFACE
TDI
TDO
TMS
TCK
TRSTB
I
IH
O
-
I
IH
I
IL
I
IL
-
JTAG Test Data Input.
-
JTAG Test Data Output.
L
JTAG Test Mode Select.
-
JTAG Test Clock.
L
JTAG Reset (active Low).
TEST CONDITION
All Ouputs have been loaded with.
Outputs
PCI
USB *
Others
* See text scheme at page 20.
Minimum
0
0
0
Maximum
50
50
15
Unit
pF
pF
pF
13/22
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