ST70137 Ver la hoja de datos (PDF) - STMicroelectronics

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componentes Descripción

Fabricante

ST70137

UNICORN™ PCI & USB CONTROLLERLESS ADSL DMT TRANSCEIVER

STMicroelectronics 

ST70137

PIN DESCRIPTION (continued)

Signal Name

PCI_CBE_N[3:0]

PCI_PAR

PCI_FRAMEN

PCI_DEVSELN

PCI_IRDYN

PCI_IDSEL

Direction Init Status Polarity

Signal Description

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

I

I

L

PCI Multiplexed Bus Command Mode

Bus command and byte enables are multiplexed on the

same pins. These pins define the current bus command

during an address phase. During a data phase, these pins

are used as Byte Enables, with PCI_CBE_N[0] (LSB)

enabling byte 0 and PCI_CBE_N[3] enabling byte 3

(MSB).

C/BE[3:0]=Command Type

0000 = Interrupt Acknowledge

0001 = Special Cycle

0010 = I/O Read

0011 = I/O Write

0100 = Reserved

0101 = Reserved

0110 = Memory Read

0111 = Memory Write

1000 = Reserved

1001 = Reserved

1010 = Configuration Read

1011 = Configuration Write

1100 = Memory Read Multiple

1101 = Memory Write Multiple

1110 = Memory Read line

1111 = Memory Write and Invalidate

H

PCI Parity (even)

Parity is always driven as even from all PCI_AD[31:0] and

PCI_CBE[3:0] signals. The parity is valid during the clock

following the address phase and is driven by the bus mas-

ter. During a data phase for write transactions, the bus

master sources this signal on the clock following

PCI_IRDYN active; during data phase for read transac-

tions, this signal is driven by the target and is valid on the

clock following PCI_TRDYN active. The PCI_PAR signal

has the same timing as PCI_AD[], delayed by one clock.

L

PCI Cycle Frame

This signal is driven by current bus master to indicate the

beginning and duration of a bus transaction. When

PCI_FRAMEN is first asserted, it indicates a bus transac-

tion is beginning with a valid addresses and bus com-

mand present on PCI_AD[31:0] and PCI_CBE[3:0]. Data

transfer continue until PCI_FRAMEN is asserted.

PCI_FRAMEN de-assertion indicates the transaction is in

final data phase or has completed.

L

PCI Device Select

This signal is driven by a target decoding and recognizing

its bus address. This signal informs a bus master whether

an agent has decoded a current bus cycle.

L

PCI Initiator Ready

This signal is always driven by the bus master to indicate

its ability to complete the current data phase. During write

transactions it indicates PCI_AD[] contains valid data.

H

PCI Initializatio n Device Select

This pin is used as chip select during configuration read

or write transactions.

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