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Fabricante

L9380
(Rev.:1998)

TRIPLE HIGH-SIDE MOSFET DRIVER

STMicroelectronics 

L9380

In application which don’t use the overload pro-

tection or if one channel is not used, the Timer pin

of this channel must be connected to ground and

the drain pin with a resistor to Vbat.

The timing characteristic illustrates the function

and the meaning of VDSmin and Toff (see figure 4).

The input current of the overload sense compara-

tor is specified as ISmax. The sum IPR + IDmax gen-

erates a drop across the external resistor RD if

the drain pin voltage is higher than the source pin

(see Fig. 5). In the switching point the comparator

input source pin currents are equal and the half of

the specified current ISmax. For an offset compen-

sation equal external resistors (RD = RS) at drain

and source pin are imperative. The drain sense

comparator, which detects the overload, has a

symmetrical hysteresis of 20mV (see Fig. 6). Ex-

ceeding the source pin voltage by 10mV with re-

spect to the drain voltage forces the timer capaci-

tor to discharge. Decreasing the source pin

voltage 10mV lower than the drain pin voltage an

overload of the external MOS is detected and the

timer capacitor will be loaded. After reaching a

voltage at pin CT higher than the timer threshold

VThi the influenced channel is switched off. In this

case the overload is stored in the timer capacitor.

The timer capacitor will be discharged with a

’High’ signal at the input (see Fig. 4). After reach-

ing the lower timer threshold VTLo the overload

protection is reset and the channel is able to

switch on again.

The application diagram is shown in Fig. 7. Be-

cause of the transients present at the power lines

during operation and possible disturbances in the

system the external resistors are necessary.

Positive ISO-Pulses at Drain, Gate Source are

clamped with an active clamping structure. The

clamping voltage is less than 60V. Negative

Pulses are only clamped with the ESD-Structure

less than -15V. This transients lower than -15V

can influence the other channels.

In order to protect the transistor against overload

and gate breakdown protection diodes between

gate and source and gate and drain has to be

connected. In case of overvoltage into VS (VS >

20V) the charge pump oscillation is stopped.

Then the charge pump capacitor will be loaded by

Figure 6. Comparator hysteresis.

VT

D98AT394

-10mV VDr +10mV

VSo

a diode and a resistor in series up to VS (see

Block Diagram). In this case the channels are not

influenced. In reverse battery condition the pins

D1, D2, S1, S2 follow the battery potential down

to -13V (high impedance) and the gate driver pins

G1, G2 is referred to S1, S2. In this way it is as-

sured that M1 and M2 will not be driven into the

linear conductive mode. This protection function

is operating for VS1, VS2 down to -15V. The gate

driver output G3 is referred to the D1 in this case.

This function guarantees that the source to

source connected N-Channel MOS transistors M3

and M4 remains OFF.

All the supplies and the in- and output of the PC-

Board are supplied with a 40 wires flat cable (not

used wires are left open). This cable is submitted

to the RF in the strip-line like described in DIN

40839-4 or ISO 11456-5.

The measured circuit was build up on a PCB

board with ground plane. In the frequency range

from 1MHz to 400MHz and 80% AM-modulation

of 1KHz with field strength of 200V/m no influence

to the basic function was detected on a typical de-

vice. The failure criteria is an envelope of the out-

put signal with 20% in the amplitude and 2% in

the time.

6/12

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