SPT7853 Ver la hoja de datos (PDF) - Signal Processing Technologies

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SPT7853

TRIPLE 10-BIT, 30 MSPS A/D CONVERTER

Signal Processing Technologies 

Force and sense taps are provided to ensure accurate and

stable setting of the upper and lower ladder sense line volt-

ages across part-to-part and temperature variations. By

using the configuration shown in figure 3, offset and gain

errors of less than ±2 LSB can be obtained.

Figure 3 – Ladder Force/Sense Circuit

+

–

VRHF

VRHS

VRLS

–

+

VRLF

All capacitors are 0.01 µF

Figure 4 – Simplified Reference Ladder Drive Circuit

without Force/Sense Circuit

+4.0 V

External

Reference

VRHS

(+3.72 V)

280 mV R/2

R

R

The reference ladder circuit shown in figure 4 is a simplified

representation of the actual reference ladder with force and

sense taps shown. Due to the actual internal structure of the

ladder, the voltage drop from VRHF to VRHS is not equivalent

to the voltage drop from VRLF to VRLS.

Typically, the top side voltage drop for VRHF to VRHS will

equal:

VRHF – VRHS = 7% of (VRHF – VRLF) (typical),

and the bottom side voltage drop for VRLS to VRLF will equal:

VRLS – VRLF = 8.8% of (VRHF – VRLF) (typical).

Figure 4 shows an example of expected voltage drops for a

specific case. VREF of 4.0 V is applied to VRHF, and VRLF is

tied to AGND. A 280 mV drop is seen at VRHS (= 3.72 V) and

a 350 mV increase is seen at VRLS (= 0.35 V).

ANALOG INPUT

The input voltage range is from VRLS to VRHS and will scale

proportionally with respect to the voltage reference. (See

voltage reference section.)

The drive requirements for the analog inputs are very mini-

mal when compared to most other converters, due to the

SPT7853’s extremely low input capacitance of only 5 pF

and very high input resistance of 50 kΩ.

The analog input should be protected through a series resis-

tor and diode clamping circuit as shown in figure 5.

Figure 5 – Recommended Input Protection Circuit

+V

AVDD

VRLS

(0.35 V)

VRLF (AGND)

(0.0 V)

R

R

R

R

350 mV R/2

R=30 Ω (typ)

All capacitors are 0.01 µF

In cases where wider variations in offset and gain can be

tolerated, VREF can be tied directly to VRHF and AGND can

be tied directly to VRLF as shown in figure 4. Decouple force

and sense lines to AGND with a 0.01 µF capacitor (chip cap

preferred) to minimize high-frequency noise injection. If this

simplified configuration is used, the following considerations

should be taken into account:

Buffer

D1

47 Ω

D2

ADC

–V

D1 = D2 = Hewlett Packard HP5712 or equivalent

SPT

7

SPT7853

12/14/99

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