CA555C Ver la hoja de datos (PDF) - Intersil
Número de pieza
componentes Descripción
Fabricante
CA555C Datasheet PDF : 6 Pages
| |||
CA555, CA555C, LM555C
Schematic Diagram
V+
THRESHOLD
COMPARATOR
8
4.7K 830
4.7K
TRIGGER
COMPARATOR
1K
5K
FLIP-FLOP
6.8K
OUTPUT
D1
D2
Q3 Q4
THRESHOLD
6
CONTROL
VOLTAGE
5
2
TRIGGER
4
RESET
7
DISCHARGE
1
V-
Q1
Q7
Q2 Q5
10K
RESET
Q8
Q6
DISCHARGE
Q10
Q16
Q19
Q20
OUTPUT
3.9K
3
7K
5K
Q11 Q12
Q9
Q13
5K
100K
4.7K
D3
D4
Q15
Q14
Q18
220
Q17
Q21
4.7K
100
NOTE: Resistance values are in ohms.
Typical Applications
Reset Timer (Monostable Operation)
Figure 1 shows the CA555 connected as a reset timer. In this
mode of operation capacitor CT is initially held discharged by
a transistor on the integrated circuit. Upon closing the “start”
switch, or applying a negative trigger pulse to terminal 2, the
integral timer flip-flop is “set” and releases the short circuit
across CT which drives the output voltage “high” (relay
energized). The action allows the voltage across the capacitor
to increase exponentially with the constant t = R1CT. When
the voltage across the capacitor equals 2/3 V+, the
comparator resets the flip-flop which in turn discharges the
capacitor rapidly and drives the output to its low state.
Since the charge rate and threshold level of the comparator
are both directly proportional to V+, the timing interval is
relatively independent of supply voltage variations. Typically,
the timing varies only 0.05% for a 1V change in V+.
Applying a negative pulse simultaneously to the reset
terminal (4) and the trigger terminal (2) during the timing
cycle discharges CT and causes the timing cycle to restart.
Momentarily closing only the reset switch during the timing
interval discharges CT, but the timing cycle does not restart.
RESET
R1
4
V+
5V
680
7
8
EO
CA555
3
1N4001
6
5
1
2
10K
RELAY
CT
4.7K
680 COIL
0.01µF
S1
START
NOTE: All resistance values are in ohms.
FIGURE 1. RESET TIMER (MONOSTABLE OPERATION)
3
Share Link: 