LTC1591-1CG(RevA) Ver la hoja de datos (PDF) - Linear Technology

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LTC1591-1CG
(Rev.:RevA)

14-Bit and 16-Bit Parallel Low Glitch Multiplying DACs with 4-Quadrant Resistors

Linear Technology 

LTC1591/LTC1597

TRUTH TABLE

Table 1

CONTROL INPUTS

CLR WR LD

0XX

100

111

101

1

110

REGISTER OPERATION

Reset Input and DAC Register to All 0s for LTC1591/LTC1597 and Midscale for LTC1591-1/LTC1597-1 (Asynchronous Operation)

Load Input Register with All 14/16 Data Bits

Load DAC Register with the Contents of the Input Register

Input and DAC Register Are Transparent

CLK = LD and WR Tied Together. The 14/16 Data Bits Are Loaded into the Input Register on the Falling Edge of the CLK and Then

Loaded into the DAC Register on the Rising Edge of the CLK

No Register Operation

BLOCK DIAGRA SM

REF 1

12k

48k

48k

48k

RCOM 2

12k

R1 3

LTC1591

48k

48k

48k

48k

48k

48k

5 RFB

96k

96k

12k

96k 96k 12k

4 ROFS

VCC 23

LD 8

DECODER

D13

D12

LOAD (MSB)

D11

D10

DAC REGISTER

D9 • • •

D0

(LSB) RST

6 IOUT1

7 AGND

22 DGND

28 CLR

WR 9

WR

10 11

D13 D12

INPUT REGISTER

RST

••••

21 24 25 26 27

D2 D1 D0 NC NC

1591 BD

15917fa

11

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