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NE56625-20 Datasheet PDF : 15 Pages
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Philips Semiconductors
System reset with Watchdog timer
Product data
NE56625-20
Timing diagram
The timing diagram shown in Figure 17 depicts the operation of the
device. Letters indicate events on the TIME axis.
A: At start-up ‘A’, the VCC voltage begins to rise. Also the RESET
and Battery Check (BC) voltages initially rise, but then abruptly
return to a LOW state. This is due to VCC reaching the level of 0.8 V
that activates the internal bias circuitry, asserting RESET and BC.
B: Just before ‘B’, the CT voltage starts to ramp up. This is caused
by, and coincident to, VCC reaching the threshold level of VSHR. At
this level the device initiates the RESET delay time, tPLH. VCC
continues to rise above VSHR.
C: At ‘C’, VCC rises to the threshold level of VSHB, the upper
voltage BC detection threshold. At this level, the BC output goes
HIGH. BC output follows VCC to its normal operating level.
D: At ‘D’, VCC is above the undervoltage detect threshold and CT
has ramped up to its upper detect level. At this point, an internal
ramp discharge transistor activates, discharging CT. Reset assertion
is still in effect since the delay time has not elapsed.
E: At ‘E’, the delay time has elapsed and the device removes the
hold on the reset. RESET goes HIGH.
In a microprocessor based system these events remove the reset
from the microprocessor, allowing it to function normally. The system
must send clock signals to the Watchdog Timer often enough to
prevent CT from ramping up to the CT threshold, to prevent reset
signals from being generated. Each clock signal discharges CT.
E–F: Midway between ‘E’ and ‘F’, the CLK signals cease allowing
the CT voltage to ramp up to its RESET threshold at ‘F’. At this time
reset signals are generated (RESET goes LOW). The device
attempts to come out of reset as the CT voltage is discharged, and
finally does come out of reset when CLK signals are reestablished
after two attempts of CT.
G–I: Immediately before ‘G’, falling VCC causes the RESET and
BC outputs to sag. CLK signals are still being received, and CT is
within normal operating range. VCC continues to sag until the VSLB
battery check undervoltage threshold is reached. At that time (G),
BC output goes LOW. VCC sags still further until VSLR reset
undervoltage threshold is reached. At this point (H), reset is
asserted and RESET goes LOW. Between ‘H’ and ‘I’, VCC starts to
rise, however, CT voltage does not start to ramp up until ‘I’, when
VCC reaches the VSHR upper reset threshold. Also, the RESET
delay is initiated.
J–K: At ‘J’, the BC output goes HIGH when VCC rises to VSHB.
Between ‘J’ and ‘K, CT reaches the upper threshold level again. At
‘K’, RESET delay time elapses and the reset is released and
RESET goes HIGH.
L–M: From ‘L’ to ‘M’, the RCT is shorted to ground. This disables
the Watchdog timer by shorting CT to ground. At other times RCT is
open or taken to VCC with a resistor of 1 MΩ or greater. This
configuration enables the Watchdog timer.
N: After ‘N’, normal CLK signals are received, but at a lower
frequency than those following event ‘D’. The frequency is above the
minimum frequency required to keep the device from outputting
reset signals.
O–P: At ‘O’, VCC is normal, CLK signals are being received, and
no reset signals are output. At event ‘P’, the VCC starts falling,
causing RESET and BC to also fall.
Q: At event ‘Q’ VCC sags to the point where the VSLR undervoltage
threshold point is reached, and at that level reset signal is outputted
(RESET to a LOW state).
R: At event ‘R’ the VCC voltage has deteriorated to a level where
normal internal circuit bias is no longer able to maintain a RESET,
and as a result may exhibit a slight rise to something less than 0.8 V.
As VCC decays even further, RESET also decreases to zero.
2003 Oct 15
10
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