LTC1261LIMS8-TRPBF Ver la hoja de datos (PDF) - Linear Technology

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LTC1261LIMS8-TRPBF

Switched Capacitor Regulated Voltage Inverter

Linear Technology 

APPLICATIONS INFORMATION

VCC

LTC1261L

CLK

650kHz

S

Q

R

S1

C1+

C1

S4

S2

C1–

S3

OUT

R2

+ COUT

R1

INTERNALLY

CONNECTED FOR

FIXED OUTPUT

VOLTAGE PARTS

ADJ (COMP)

COMP1

REG

+

60mV

VREF = 1.23V

1.17V

COMP2

–

VOUT

Figure 1. Block Diagram

1261L F01

OUTPUT RIPPLE

Output ripple in the LTC1261L is present from two sources;

voltage droop at the output capacitor between clocks and

frequency response of the regulation loop. Voltage droop

is easy to calculate. With a typical clock frequency of

650kHz, the charge on the output capacitor is refreshed

once every 1.54µs. With a 15mA load and a 3.3µF output

capacitor, the output will droop by:

ILOAD





∆t

COUT





=

15mA





1.54µs

3.3µF





=

7mV

This can be a significant ripple component when the output

is heavily loaded, especially if the output capacitor is small.

If absolute minimum output ripple is required, a 10µF or

greater output capacitor should be used.

Regulation loop frequency response is the other major

contributor to output ripple. The LTC1261L regulates the

output voltage by limiting the amount of charge trans-

ferred to the output capacitor on a cycle-by-cycle basis.

The output voltage is sensed at the ADJ pin (COMP for

fixed output voltage versions) through an internal or

external resistor divider from the OUT pin to ground. As

the flying capacitor is first connected to the output, the

output voltage begins to change quite rapidly. As soon as

it exceeds the set point COMP1 trips, switching the state

of the charge pump and stopping the charge transfer.

Because the RC time constant of the capacitors and the

switches is quite short, the ADJ pin must have a wide AC

bandwidth to be able to respond to the output in time.

External parasitic capacitance at the ADJ pin can reduce

the bandwidth to the point where the comparator cannot

respond by the time the clock pulse finishes. When this

happens the comparator will allow a few complete pulses

through, then overcorrect and disable the charge pump

until the output drops below the set point. Under these

conditions the output will remain in regulation but the

output ripple will increase as the comparator “hunts” for

the correct value.

To prevent this from happening, an external capacitor can

be connected from ADJ (or COMP for fixed output voltage

parts) to ground to compensate for external parasitics and

1261lfa

7

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