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LTC1261L

Switched Capacitor Regulated Voltage Inverter

Linear Technology 

LTC1261L

APPLICATIONS INFORMATION

tailored to the application. Reducing the value of the flying

capacitor reduces the amount of charge transferred with

each clock cycle. This limits maximum output current, but

also cuts the size of the voltage step at the output with each

clock cycle. The smaller capacitor draws smaller pulses

of current out of VCC as well, limiting peak currents and

reducing the demands on the input supply. Table 1 shows

recommended values of flying capacitor vs maximum

load capacity.

Table 1. Typical Max Load (mA) vs Flying Capacitor Value at

TA = 25°C, VOUT = –4V

FLYING CAPACITOR VALUE (µF)

MAX LOAD (mA)

VCC = 5V

0.1

20

0.047

15

0.033

10

0.022

5

0.01

1

The output capacitor performs two functions: it provides

output current to the load during half of the charge pump

cycle and its value helps to set the output ripple voltage.

For applications that are insensitive to output ripple, the

output bypass capacitor can be as small as 1µF. Larger

output capacitors will reduce output ripple further at the

expense of turn-on time.

Capacitor ESR

Output capacitor Equivalent Series Resistance (ESR) is

another factor to consider. Excessive ESR in the output

capacitor can fool the regulation loop into keeping the

output artificially low by prematurely terminating the

charging cycle. As the charge pump switches to recharge

the output a brief surge of current flows from the flying

capacitors to the output capacitor. This current surge can

be as high as 100mA under full load conditions. A typical

3.3µF tantalum capacitor has 1Ω or 2Ω of ESR; 100mA

× 2Ω = 200mV. If the output is within 200mV of the set

point this additional 200mV surge will trip the feedback

comparator and terminate the charging cycle. The pulse

dissipates quickly and the comparator returns to the

correct state, but the RS latch will not allow the charge

pump to respond until the next clock edge. This prevents

the charge pump from going into very high frequency

oscillation under such conditions but it also creates an

output error as the feedback loop regulates based on

the top of the spike, not the average value of the output

(Figure 4). The resulting output voltage behaves as if a

resistor of value CESR × (IPK/IAVE)Ω was placed in series

with the output. To avoid this nasty sequence of events,

connect a 0.1µF ceramic capacitor in parallel with the

larger output capacitor. The ceramic capacitor will “eat”

the high frequency spike, preventing it from fooling the

feedback loop, while the larger but slower tantalum or

aluminum output capacitor supplies output current to the

load between charge cycles.

CLOCK

LOW ESR

OUTPUT CAP

VOUT

HIGH ESR

OUTPUT CAP

VOUT

VSET

VOUT

AVERAGE

COMP1

OUTPUT

VSET

VOUT

AVERAGE

COMP1

OUTPUT

1261L F04

Figure 4. Output Ripple with Low and High ESR Capacitors

Note that ESR in the flying capacitor will not cause the same

condition; in fact, it may actually improve the situation by

cutting the peak current and lowering the amplitude of the

spike. However, more flying capacitor ESR is not neces-

sarily better. As soon as the RC time constant approaches

half of a clock period (the time the capacitors have to share

charge at full duty cycle) the output current capability of the

LTC1261L starts to diminish. For a 0.1µF flying capacitor,

this gives a maximum total series resistance of:

1

2





tCLK

CFLY





=

1

2





1

650kHz





/

0.1µF

=

7.7Ω

Most of this resistance is already provided by the internal

switches in the LTC1261L. More than 1Ω or 2Ω of ESR

on the flying capacitors will start to affect the regulation

at maximum load.

1261lfa

9

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