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Fabricante

LTC1261L

Switched Capacitor Regulated Voltage Inverter

Linear Technology 

LTC1261L

TEST CIRCUITS

Fixed Output

5V

+

10µF

0.1µF

1 VCC

SHDN 8

2 C1+

REG 7

3

LTC1261L-X

C1–

OUT

6

VOUT = – 4V (LTC1261L-4)

VOUT = – 4.5V (LTC1261L-4.5)

4 GND COMP 5 + 3.3µF

1261L TCO1

Adjustable Output

VCC

0.1µF

1 VCC

SHDN 8

2 C1+

REG 7

3

LTC1261L

C1–

OUT

6

4 GND

ADJ 5

VOUT

+ 3.3µF

1261L TCO2

APPLICATIONS INFORMATION

The LTC1261L uses an inverting charge pump to generate

a regulated negative output voltage that is either equal to

or less than the supply voltage. The LTC1261L needs only

three external capacitors and is available in the MSOP and

SO-8 packages

THEORY OF OPERATION

A block diagram of the LTC1261L is shown in Figure 1.

The heart of the LTC1261L is the charge pump core shown

in the dashed box. It generates a negative output voltage

by first charging the flying capacitor (C1) between VCC

and ground. It then connects the top of the flying capaci-

tor to ground, forcing the bottom of the flying capacitor

to a negative voltage. The charge on the flying capacitor

is transferred to the output bypass capacitor, leaving it

charged to the negative output voltage. This process is

driven by the internal 650kHz clock.

Figure 1 shows the charge pump configuration. With the

clock low, C1 is charged to VCC by S1 and S3. At the next

rising clock edge, S1 and S3 are open and S2 and S4

closed. S2 connects C1+ to ground, C1– is connected to

the output by S4. The charge in C1 is transferred to COUT,

setting it to a negative voltage.

The output voltage is monitored by COMP1 which com-

pares a divided replica of the output at ADJ (COMP for

fixed output voltage parts) to the internal reference. At the

beginning of a cycle the clock is low, forcing the output

of the AND gate low and charging the flying capacitor.

6

The next rising clock edge sets the RS latch, setting the

charge pump to transfer charge from the flying capacitor

to the output capacitor. As long as the output is below the

set point, COMP1 stays low, the latch stays set and the

charge pump runs at the full 50% duty cycle of the clock

gated through the AND gate. As the output approaches the

set voltage, COMP1 will trip whenever the divided signal

exceeds the internal 1.23V reference relative to OUT.

This resets the RS latch and truncates the clock pulses,

reducing the amount of charge transferred to the output

capacitor and regulating the output voltage. If the output

exceeds the set point, COMP1 stays high, inhibiting the

RS latch and disabling the charge pump.

COMP2 also monitors the divided signal at ADJ but it is

connected to a 1.17V reference, 5% below the main refer-

ence voltage. When the divided output exceeds this lower

reference voltage indicating that the output is within 5%

of the set value, COMP2 goes high turning on the REG

output transistor. This is an open-drain N-channel device

capable of sinking 4mA with a 3.3V VCC and 5mA with a

5V VCC. When in the “off” state (divided output is more

than 5% below VREF) the drain can be pulled above VCC

without damage up to a maximum of 6V above ground.

Note that the REG output only indicates if the magnitude of

the output is below the magnitude of the set point by 5%

(i.e., VOUT > –4.75V for a –5V set point). If the magnitude

of the output is forced higher than the magnitude of the

set point (i.e., to –5.25V when the output is set for –5V)

the REG output will stay low.

1261lfa

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