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Fabricante

SMJ28F010B

131072 BY 8-BIT FLASH MEMORY

Austin Semiconductor 

flow charts (continued)

SMJ28F010B

131072 BY 8-BIT

FLASH MEMORY

SGMS738 – APRIL 1998

Start

Address = 00h

VCC = 5 V ± 10%, VPP = 12 V ± 5%

X=1

Setup

Bus

Operation

Command

Initialize

Address

Comments

Standby

Wait for VPP to ramp to

VPPH (see Note A)

Initialize pulse count

Write Set-Up-Program Command

Increment

Address

Write Data

Wait = 10 µs

X=X+1

Write Program-Verify Command

Wait = 6 µs

No

Read Fail

and Verify

Byte

X = 25?

Write

Write

Standby

Write

Standby

Pass

Yes

Interactive

Mode

Read

No

Last

Address

?

Yes

Write Read Command

Apply VPPL

Device Passed

Apply VPPL

Power

Down

Device Failed

—

Write

Standby

Set-Up-

Program

Write

Data = 40h

Write Data Valid address / data

Wait = 10 µs

Program- Data = C0h; ends

Verify

program operation

Wait = 6 µs

Read byte to verify

programming; compare

output to expected output

—

—

Read

Data = 00h; resets register

for read operations

Wait for VPP to ramp to

VPPL (see Note B)

NOTES: A. See the recommended operating conditions for the value of VPPH.

B. See the recommended operating conditions for the value of VPPL.

Figure 1. Algorithm-Selection Programming Flow Chart

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