MSM54V25632A-10AGBK4 Ver la hoja de datos (PDF) - Oki Electric Industry

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MSM54V25632A-10AGBK4

131,072-Word x 32-Bit x 2-Bank Synchronous Graphics RAM

Oki Electric Industry 

¡ Semiconductor

MSM54V25632A

COMMAND OPERATION

Mode Register Set Command (CS, RAS, CAS, WE, DSF = "Low")

The MSM54V25632A has the mode register that defines the operation mode "CAS Latency,

Burst Length, Burst Sequence". The mode register is composed of ten bits of memories

corresponding to address inputs A0 - A8 and BA. The Mode Register Set command should be

executed just after the MSM54V25632A is powered on. Before entering this command, all banks

must be precharged. Next command can be issued after tRSC.

Special Mode Register Set Command (CS, RAS, CAS, WE = "Low", DSF = "High")

The MSM54V25632A has the 32-bit color register for block write operation and the 32-bit mask

register for write per bit operation. The Special Mode Register Set command performs loading

mask register or color register. When A5 is "high", The mask data presented on the DQ0 - DQ31

is latched into the mask register. When A6 is "high", The color data presented on the DQ0 - DQ31

is latched into the color register. The Special Mode Register Set command must be executed

before Masked Block Write and Write Per Bit operations. Next command can be issued after

tRSC.

Auto Refresh Command (CS, RAS, CAS, DSF = "Low", WE, CKE = "High")

The Auto Refresh command performs refresh automatically by the address counter. The refresh

operation must be performed 1024 times within 16 ms and the next command can be issued after

tRC from last Auto Refresh command. Before entering this command, all banks must be

precharged.

Self Refresh Entry/Exit Command (CS, RAS, CAS, DSF, CKE = "Low", WE = "High")

The self refresh operation continues after the Self Refresh Entry command is entered, with CKE

level left "low". This operation terminates by making CKE level "high". The self refresh

operation is performed automatically by the internal address counter on the MSM54V25632A

chip. In self refresh mode, no external refresh control is required. Before entering self refresh

mode, all banks must be precharged. Next command can be issued after tRC.

Single Bank Precharge Command (CS, RAS, WE, DSF, A8 = "Low", CAS = "High")

The Single Bank Precharge command triggers bank precharge operation. Precharge bank is

selected by BA.

All Banks Precharge Command (CS, RAS, WE, DSF = "Low", CAS, A8 = "High")

The All Bank Precharge command triggers precharge of both bank A and bank B.

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