MSM54V32126-60GS-K Ver la hoja de datos (PDF) - Oki Electric Industry

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MSM54V32126-60GS-K

131,072-Word x 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO

Oki Electric Industry 

¡ Semiconductor

MSM54V32126/8

Notes:

1. An initial pause of 200 ms is required after power-up followed by any 8 RAS cycles

(Example : RAS only refresh) before proper device operation is achieved. In case of

using internal refresh counter, a minimum of 8 CAS before RAS cycles instead of 8 RAS

cycles are required.

2. The AC characteristics assume at tT = 3 ns.

3. VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals.

Also, transition times are measured between VIH and VIL. Input levels at the AC testing

are 3.0 V/0 V.

4. Data outputs are measured with a load of 30 pF.

DOUT reference levels : VOH/VOL = 2.0 V/0.8 V.

5. tREZ (Max.), tCEZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the

outputs achieve the open circuit condition and are not referenced to output voltage

levels. This parameter is sampled and not 100% tested.

6. Either tRCH or tRRH must be satisfied for a read cycle.

7. These parameters are referenced to CAS leading edge of early write cycles and to WE

leading edge in OE controlled write cycles and read modify write cycles.

8. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included

in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), the cycle is an

early write cycle and the data out pin will remain open circuit throughout the entire

cycle; If tRWD ≥ tRWD (Min.), tCWD ≥ tCWD (Min.) and tAWD ≥ tAWD (Min.), the cycle is

a read modify write cycle and the data out will contain data read from the selected cell:

If neither of the above sets of conditions is satisfied, the condition of the data out is

indeterminate.

9. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.

tRCD (Max.) is specified as a reference point only: If tRCD is greater than the specified

tRCD (Max.) limit, then access time is controlled by tCAC.

10. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.)

is specified as a reference point only: If tRAD is greater than the specified tRAD (Max.)

limit, then access time is controlled by tAA.

11. This is guaranteed by design. (tDOH = tCAC - output transition time) This parameter is

not 100% tested.

12. These parameters are determined by the earliest falling edge of CAS1, CAS2, CAS3, or

CAS4.

13. These parameters are determined by the latest rising edge of CAS1, CAS2, CAS3, or

CAS4.

14. tCWL should be satisfied by all CASes.

15. tCP and tCPT are determined by the time that all CASes are high.

16. Only MSM54V32128.

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