MTV018N Ver la hoja de datos (PDF) - Myson Century Inc
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MTV018N Datasheet PDF : 16 Pages
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MYSON
TECHNOLOGY
MTV018
VCLK Freq = HFLB Freq * HORR * 12
The VCLK frequency ranges from 6MHz to 96MHz selected by (VCO1, VCO0). In addition, when HFLB input
is not present to MTV018, the PLL will generate a specific system clock, approximately 2.5MHz, by a built-in
oscillator to ensure data integrity.
3.6 Display & Row control registers
The internal RAM contains display and row control registers. The display registers have 450 locations which
are allocated between (row 0, column 0) to (row 14, column 29), as shown in Figure 4. Each display register
has its corresponding character address on ADDRESS byte, and 1 blink bit and its corresponding color bits on
ATTRIBUTE bytes. The row control register is allocated at column 30 for row 0 to row 14, it is used to set
character size to each respective row. If double width character is chosen, only even column characters could
be displayed on screen and the odd column characters will be hidden.
ROW #
01
0
1
13
14
COLUMN #
DISPLAY
REGISTERS
28 29
30
31
R
E
S
ROW
E
CTRL REG R
V
E
D
COLUMN#
ROW 15 02
35
68
911
1218
1926
WINDOW1 WINDOW2 WINDOW3 WINDOW4 FRAME PWM D/A
CRTL REG CRTL REG
3.6.1 Register descriptions
FIGURE 4. Memory map
1. Display Register, (Row 0 - 14, Column 0 - 29)
ADDRESS BYTE
b7
b6
b5
b4
b3
b2
b1
b0
MSB
CRADDR
LSB
CRADDR - Define ROM character and user programmable fonts address.
(a) 0 ~ 247 ⇒ 248 build-in characters and graphic symbols.
(b) 248 ~ 255 ⇒ 8 user programmable fonts.
ATTRIBUTE BYTE
b7
b6
b5
b4
b3
b2
b1
b0
-
-
-
-
BLINK R1
G1
B1
7/16
MTV018 Revision 4.0 10/21/1999
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