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STPCI2HEYC

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

1.7. CLOCK TREE

The STPC Atlas integrates many features and

generates all its clocks from a single 14MHz

oscillator. This results in multiple clock domains as

described in Figure 1-2.

Figure 1-2. STPC Atlas clock architecture

The speed of the PLLs is either fixed (DEVCLK),

either programmable by strap option (HCLK)

either programmable by software (DCLK, MCLK).

When in synchronized mode, MCLK speed is fixed

to HCLKO speed and HCLKI is generated from

MCLKI.

VCLK

DCLK

MCLKO

MCLKI

) VIP

ct(s CRTC,Video,TFT

rodu 48MHz DEVCLK

P PLL

DCLK

PLL

MCLK

PLL

SDRAM controller

GE, LDE, AFE

HCLK HCLKO

PLL

Obsolete 1/6

- UARTs

) 1/26

ct(s 1/4

USB

rodu 1/2

Obsolete P// Port

ISA

CPU

x2

PCMCIA

IPC

North Bridge

Kbd/Mouse

Host

South Bridge

Local Bus

PWM

1/2

1/3

1/2 1/4

HCLKI

DEVCLK

(24MHz)

XTALO

XTALI

14.31818 MHz

OSC14M ISACLK

(14MHz)

PCICLKI

HCLK

PCICLKO

11/108

1

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