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STA002

STARMAN™ CHANNEL DECODER

STMicroelectronics 

STA002

1.5.5 TDM_MULTIPLEX Registers (continued)

HEX_COD

22EH

22FH

230H

231H

232H

233H

234H

235H

236H

237H

23CH

23DH

237EH

DEC_COD

558

559

560

561

562

563

564

565

566

567

568

569

570

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

TEST_PURPOSE

TEST_PURPOSE

TEST_PURPOSE

REGISTER NAME

1.5.6 TSCC_MEM Registers

HEX_COD DEC_COD

300H

301H

302H

303H

304H

305H

306H

307H

768

TSCW 1 (7:0)

769

TSCW 1 (15:8)

770

TSCW 2 (7:0)

771

TSCW 2 (15:8)

772

TSCW 3 (7:0)

773

TSCW 3 (15:8)

774

TSCW 4 (7:0)

775

TSCW 4 (15:8)

REGISTER NAME

TYPE

R

R

R

R

R

R

R

R

R

R

R

R

R

RESET

VALUE

0EH

12H

32H

0CH

1CH

2FH

0AH

0BH

2AH

09H

09H

09H

09H

TYPE

R

R

R

R

R

R

R

R

RESET

VALUE

3BCH

3BDH

3BEH

3BFH

3C0H

3C1H

956

TSCW 95 (7:0)

957

TSCW 95 (15:8)

958

TSCW 96 (7:0)

959

TSCW 96 (15:8)

960

TSCW ID (7:0)

961

TSCW ID (15:8)

2. IF INTERFACE

The Master Clock (M_CLK) is the source of all

the STA002 internal timings.

M_CLK is internally divided to drive the A/D con-

verter and to provide the clock signal for the

QPSK block.

The IF input signal, centered at 1.84MHz, is over-

sampled at a frequency Fck of M_CLK/4 or

M_CLK/2 according to STA002 presettings.

2.1 PLL

This fully integrated PLL includes the phase/fre-

quency detector, the charge pump, the filter and

R

R

R

R

R

R

the VCO.

The PLL output frequency Fck can be selected via

I2C interface according to the PLL_INT_REG.

Reg. name: PLL_INT_REG

Internal address: 21E H

Reset Value : 00H

Type: R/W

MSB

LSB

X X b5 b4 b3 b2 b1 b0

Description: PLL and INTR pin control register

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