WED9LC6416V1510BC Ver la hoja de datos (PDF) - White Electronic Designs => Micro Semi
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WED9LC6416V1510BC Datasheet PDF : 27 Pages
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WED9LC6416V
SSRAM OPERATION TRUTH TABLE
Operation
Deselected Cycle, Power Down
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
Address Used
None
External
External
External
Current
Current
Current
Current
Current
Current
SSCE
H
L
L
L
X
X
H
H
X
H
SSADS
L
L
L
L
H
H
H
H
H
H
SSWE
X
L
H
H
H
H
H
H
L
L
SSOE
X
X
L
H
L
H
L
H
X
X
DQ
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
NOTE:
1. X means “don’t care”, H means logic HIGH. L means logic LOW.
2. All inputs except SSOE must meet setup and hold times around the rising edge (LOW to HIGH) of SSCLK.
3. Suspending burst generates wait cycle
4. For a write operation following a read operation, SSOE must be HIGH before the input data required setup time plus High-Z time for SSOE and staying HIGH
though out the input data hold time.
5. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
SSRAM PARTIAL TRUTH TABLE
Function
READ
WRITE one Byte (DQ0-7)
WRITE all Bytes
SSWE
H
L
L
BWE0
X
L
L
BWE1 BWE2
XX
HH
L
L
BWE3
X
H
L
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
6
January 2001
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