MAX3100ETG-T Ver la hoja de datos (PDF) - Maxim Integrated
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MAX3100ETG-T Datasheet PDF : 24 Pages
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MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
MAX3100 Operations
Write Operations
Table 1 shows write-configuration data. A 16-bit
SPI/MICROWIRE write configuration clears the receive
FIFO and the R, T, RA/FE, D0r–D7r, D0t–D7t, Pr, and Pt
registers. RTS and CTS remain unchanged. The new
configuration is valid on CS’s rising edge if the transmit
buffer is empty (T = 1) and transmission is over. If the
latest transmission has not been completed, the regis-
ters are updated when the transmission is over (T = 0).
The write-configuration bits (FEN, SHDNi, IR, ST, PE, L,
B3–B0) take effect after the current transmission is
over. The mask bits (TM, RM, PM, RAM) take effect
immediately after the 16th clock’s rising edge at SCLK.
Read Operations
Table 2 shows read-configuration data. This register
reads back the last configuration written to the
MAX3100. The device enters test mode if bit 0 = 1. In
this mode, if CS = 0, the RTS pin acts as the 16x clock
generator’s output. This may be useful for direct baud-
rate generation (in this mode, TX and RX are in digital
loopback).
Normally, the write-data register loads the TX-buffer
register. To change the RTS pin’s state without writing
data, set the TE bit. Setting the TE bit high inhibits the
write command (Table 3).
Reading data clears the R bit and interrupt IRQ (Table 4).
Register Functions
Table 5 shows read/write operation and power-on reset
state (POR), and describes each bit used in program-
ming the MAX3100. Figure 5 shows parity and word-
length control.
Table 1. Write Configuration (D15, D14 = 1, 1)
BIT 15 14 13
12
11 10
9
8
7
6
5
4
3
2
1
0
DIN
1
1 FEN SHDNi TM RM PM RAM IR ST PE L B3 B2 B1 B0
DOUT R
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 2. Read Configuration (D15, D14 = 0, 1)
BIT 15 14 13
12
11 10 9
8
7
6
5
4
3
2
1
0
DIN
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0 TEST
DOUT R
T FEN SHDNo TM RM PM RAM IR ST PE L B3 B2 B1 B0
Table 3. Write Data (D15, D14 = 1, 0)
BIT 15 14 13 12 11
10
9
8
DIN
1
0
0
0
0
TE RTS Pt
DOUT R
T
0
0
0 RA/FE CTS Pr
7
6
5
4
3
2
1
0
D7t D6t D5t D4t D3t D2t D1t D0t
D7r D6r D5r D4r D3r D2r D1r D0r
Table 4. Read Data (D15, D14 = 0, 0)
BIT 15 14 13 12 11
10
9
8
7
6
5
4
3
2
1
0
DIN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DOUT R
T
0
0
0 RA/FE CTS Pr D7r D6r D5r D4r D3r D2r D1r D0r
8
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