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MAX3100CEE-T Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza
componentes Descripción
Fabricante
MAX3100CEE-T
MaximIC
Maxim Integrated MaximIC
MAX3100CEE-T Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
AC TIMING (Figure 1)
CS Low to DOUT Valid
CS High to DOUT Tri-State
CS to SCLK Setup Time
CS to SCLK Hold Time
SCLK Fall to DOUT Valid
DIN to SCLK Setup Time
DIN to SCLK Hold Time
SCLK Period
SCLK High Time
SCLK Low Time
SCLK Rising Edge
to CS Falling
SYMBOL
CONDITIONS
tDV
tTR
tCSS
tCSH
tDO
tDS
tDH
tCP
tCH
tCL
tCS0
CLOAD = 100pF
CLOAD = 100pF, RCS = 10kΩ
CLOAD = 100pF
(Note 1)
MIN TYP
100
0
100
0
238
100
100
100
MAX
100
100
100
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS Rising Edge
to SCLK Rising
tCS1 (Note 1)
200
ns
CS High Pulse Width
tCSW
200
ns
Output Rise Time
tr
TX, RTS, DOUT: CLOAD = 100pF
10
ns
Output Fall Time
tf
TX, RTS, DOUT, IRQ: CLOAD = 100pF
10
ns
Note 1: tCS0 and tCS1 specify the minimum separation between SCLK rising edges used to write to other devices on the SPI bus
and the CS used to select the MAX3100. A separation greater than tCS0 and tCS1 ensures that the SCLK edge is ignored.
CS
SCLK
DIN
DOUT
tCSS
tCSH
tDS
tDH
tDV
•••
tCH
tCL
•••
•••
•••
Figure 1. Detailed Serial-Interface Timing
tCSH
tDO
tTR
Maxim Integrated
3

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