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VSC9142UK

STS-48c Packet/ATM Over SONET/SDH Device With Integrated Mux/Demux and Clock and Data Recovery

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

STS-48c Packet/ATM Over SONET/SDH Device

With Integrated Mux/Demux and Clock and Data Recovery

Preliminary Datasheet

VSC9142

• Two identical, but independent, special purpose ports are provided for the insertion of special purpose

bytes into the SONET/SDH transport overhead and of certain SONET/SDH alarms specific to automatic

protection switching (APS) applications.

• The entire transport overhead is captured from the serial input ports TTOH[3..0]. The captured data can

be selectively inserted into the corresponding overhead bytes of the transmitted SONET/SDH frame.

SONET/SDH Section Trace Buffers (SSTB)

• Three different Section Trace Message (J0) formats are supported in both transmit and receive directions:

one byte (SONET) message, 16 byte (SDH) message, and 64 byte (SONET CLLI) message.

• The received section trace message is checked for persistency. A mismatch alarm is supported.

CPU Interface

• All configuration bits are both writeable and readable and can be accessed regardless of the device clock

source status, except for the reset state. Configuration bits include selection bits, interrupt masking bits,

and programmable counter/control values.

• Eight programmable General Purpose Input/Output (GPIO) ports are available for monitoring and con-

trolling external signals. All GPIOs support bistable interrupts when configured as input ports.

• Clock activity monitors are implemented for all input clocks.

Bit Error Rate Monitoring

• Bit error rate monitoring is based on the Line BIP (B2) error code and is capable of measuring BERs

down to 10-10 .

• There are four independent BER monitors with individual accumulation periods and alarm thresholds.

• A saturation threshold is implemented for each BER monitor to specify the maximum number of errors

that can be accumulated per frame.

• The BER Signal Degrade (BER-SD) alarm is based on BER monitors 1 and 2.

• The BER Signal Fail (BER-SF) alarm is based on BER monitors 3 and 4.

JTAG

• Standard IEEE 1149.1 compliant JTAG interface.

Loopback Modes

• Equipment loopback is supported by looping the output from the Transmit Section Overhead Processor

(TSOP), in the transmit direction, back to the input of the Receive Section Overhead Processor (RSOP),

in the receive direction.

• Facility loopback is supported by looping the data received on the receive Line Side Interface back to the

transmit Line Side Interface.

• Section loopback is supported by looping the output from the Recieve Section Overhead Processor

(RSOP) in the receive direction back to the input of the Transmit Section Overhead Processor (TSOP), in

the transmit direction.

Page 10

 VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52319-0, Rev. 3.1

6/12/00

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