LZ9GG33M Ver la hoja de datos (PDF) - Sharp Electronics

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componentes Descripción

Fabricante

LZ9GG33M

Single chip driver IC (270K/320K pixels B/W CCD)

Sharp Electronics 

SHARP

LZ9GG33M

8

(LZ9GG33M

No, Symbol I/O Pal.

Pin Name

40 FR 36MA31 Reset pulse

41 FH2B 36MA2 lJ Hor. transfer

pulse 2B

42 FH2 36MA3 m Hor. transfer

pulse 2

43 GND - - Ground

44 FH1 36MA3 m Hor. transfer

pulse 1

45 FHlB 36MA2 jlj Hor. transfer

pulse 1B

46 OSCI OSCI - Clock input

47 OSCO OSCC - Clock output

48 NINT ICD - Non-interlace

select

L

Description

A reset pulse for CCD.

Connect to #R of CCD through the D.C. offset

circuit.

A horizontal transfer pulse for CCD.

Connect to $HZB of CCD.

A horizontal transfer pulse for CCD.

Connect to #HZ of CCD.

A grounding pin.

A horizontal transfer pulse for CCD.

Connect to #Hl of CCD.

A horizontal transfer pulse for CCD.

Connect to OHlB of CCD.

An input pin for reference clock oscillation.

Connect to OSCO(pin 47) with R.

The frequencies are as follows :

at EIA mode : 19.0699MHz (1212fH)

at CCIR mode : 19.3125MHz (1236fH)

fH=Hor. frequency

An output pin for reference clock oscillation,

The output is the inverse OSCI(pin 46).

An input pin to select non-interlace mode.

L level : Interlace mode

H level or open : Non-interlace mode

Period of Field (at non-interlace mode)

TV mode

Field

number of line

EIA

ODD

2628

CCIR

1st

312H

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