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CXD2721Q-1

Single-Chip Digital Signal Processor for Karaoke

Sony Semiconductor 

CXD2721Q-1

Item

RVDT setup time relative to SCK rise

RVDT data hold time from SCK rise

SCK Low level width

SCK High level width

XLAT Low level width

XLAT High level width

SCK rise preceding time relative to XLAT rise

SCK rise wait time relative to XLAT rise

Delay time to REDY fall relative to XLAT rise

Delay time to REDY fall relative to SCK rise

REDY fall preceding time relative to SCK rise

REDY rise preceding time relative to XLAT rise

REDY rise preceding time relative to SCK fall

XLAT fall wait time relative to SCK rise

XLAT fall delay time relative to REDY fall

Delay time from XLAT rise until TRDT data becomes active

Delay time from SCK rise until TRDT data becomes high-impedance

Delay time from SCK fall until TRDT data is established

SCK rise wait time for next transfer

Symbol

tDS

tDH

tSWL

tSWH

tLWL

tLWH

tSLP

tLSD

tLBD

tSBD

tBSP

tRLP

tRSDP

tSLD

tLDR

tLDN

tSDF

tSDD

tSS

Note 1) t is the cycle of 2/3 the clock frequency applied to the XTLI pin. (512fs)

Note 2) REDY and TRDT pins are the values for CL = 60pF.

Min.

20

1t + 20

1t + 20

1t + 20

1t + 20

1t + 20

20

3t + 20

20

20

20

3t + 20

20

2t + 40

Max. Unit

ns

ns

ns

ns

ns

ns

ns

ns

3t + 50 ns

4t + 50 ns

ns

ns

ns

ns

ns

3t + 80 ns

3t + 80 ns

2t + 70 ns

ns

–9–

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