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P83C591

Single-chip 8-bit microcontroller with CAN controller

Philips Electronics 

Philips Semiconductors

Single-chip 8-bit microcontroller with CAN controller

Preliminary Specification

P8xC591

SYMBOL

P2.0/A08 to

P2.7/A15

PSEN

ALE/PROG

EA/VPP

P0.0/AD0 to

P0.7/AD7

AVref+

AVSS

PIN

QFP44 PLCC44

DESCRIPTION

18 to 25 24 to 31 Port 2 (P2.0 to P2.7): 8-bit programmable I/O port lines;

A08 to A15: High-order address byte for external memory.

Alternate function: High-order address byte for external memory (A08-A15).

Port 2 is also used to input the upper order address during EPROM

programming and verification. A8 is on P2.0, A9 on P2.1, through A12 on

P2.4.

During reset, Port 2 will be asynchronously driven HIGH.

Port 2 has four output modes selected on a per bit basis by writing to the

P2M1 and P2M2 registers as follows:

P2M1.x P2M2.x Mode Description

0

0 Pseudo-bidirectional (standard c51 configuration default)

0

1 Push-Pull

1

0 High impedance

1

1 Open drain

26

32

Program Store Enable output: read strobe to the external Program Memory

via Ports 0 and 2. Is activated twice each machine cycle during fetches from

external Program Memory. When executing out of external Program Memory

two activations of PSEN are skipped during each access to external Data

Memory. PSEN is not activated (remains HIGH) during no fetches from

external Program Memory. PSEN can sink/source 8 LSTTL inputs. It can

drive CMOS inputs without external pull-ups.

27

33

Address Latch Enable output. Latches the low byte of the address during

access of external memory in normal operation. It is activated every six

oscillator periods except during an external Data Memory access. ALE can

sink/source 8 LSTTL inputs. It can drive CMOS inputs without an external

pull-up. To prohibit the toggling of ALE pin (RFI noise reduction) the bit A0

(SFR: AUXR.0) must be set by software; see Table 4.

PROG: the programming pulse input; alternative function for the P87C591.

29

30 to 37

35

36 to 43

External Access input. If, during reset, EA is held at a TTL level HIGH the

CPU executes out of the internal Program Memory. If, during reset, EA is held

at a TTL level LOW the CPU executes out of external Program Memory via

Port 0 and Port 2. EA is not allowed to float. EA is latched during reset and

don’t care after reset.

VPP: the programming supply voltage; alternative function for the P87C591.

Port 0: 8-bit open-drain bidirectional I/O port.

During reset, Port 0 is HIGH-Impedance (Tri-State).

AD7 to AD0: Multiplexed Low-order address and Data bus for external

memory. During these accesses internal pull-ups are activated. Port 0 can

sink/source up to 8 LSTTL inputs.

38

44

Analog to Digital Conversion Reference Resistor: High-end.

39

1

Analog ground.

2000 Jul 26

10

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