SAN3020 Ver la hoja de datos (PDF) - South African Micro Electronic Systems

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SAN3020

SINGLE CHIP TELEPHONE POWER EXTRACTION FOR EXTERNAL LOADS

South African Micro Electronic Systems 

SAN3020

When driving external loads by extracting power from the available line current, care must be taken not to affect

both DC and AC impedance. The extracted voltage should be independent from line current (assuming a line

current >20mA).

The application shown will shut off the external load when going on-hook and power-up the load when going off-

hook.

The current driving capability depends on the available line current, higher line currents allow higher driving

currents. At minimum line current (20mA), the maximum load current is ≈15mA (see pt.6 for further details).

6 Hardware configuration

Only 4 external components , shown in the dotted area (1 general purpose PNP transistor:Bmin=250, 1 general

purpose diode , 1 resistor and 1 pol. capacitor) must be added to the standard SA253x application to get a high

efficiency power extraction for external loads with the features described in pt.5 above.

When updating an existing circuit, the connection from pin #25 (= CS, SA253x) to the shunt transistor’s base (in

most applications = Q3) must be opened and a diode (D5) installed. All further components are simply added to the

circuit.

7 Circuit description

The shunt transistor (Q3) is regulating the voltage at LI ( #27) to ≈ 4.5V. Consequently, the voltage at CS ( #25) is

VLI - VBE. When adding D5, the voltage drop between LI and CS is Vconst = 2x VBE. This constant voltage provides

the base current of the power extraction transistor Q5 via R22.

The maximum load current also depends on the gain (B= IC / IB) of the transistor used. The transistor used should

have a B of ≥250 . Transistors with lower gain may also be used, but the maximum load current may be lower.

7.1 Minimum output voltage with high signals on line:

As shown in the diagram (pt. 9), the output voltage at high load currents will drop with high transmit or receive

signals on line, since the load is not supplied during the negative half-wave of the line signal. The diagram shows

the Vout/ILoad curves with no AC signal at line and with a constant AC line signal of 1Vpeak.

In practical use, an AC signal of 2Vpp is not present continuously, so the effective output voltage will be higher. It is

also possible to buffer the voltage drop during line signal bursts by increasing the value of capacitor C19.

However, the voltage decrease with high signal bursts on line should be taken into consideration when the load

voltage must not drop below a certain value.

8 Connecting loads at VDD

Small loads can also be connected at VDD directly, as long as the following rules are observed:

1. When on-hook, the load must only draw <1µA , because it is connected in parallel to the VDD -cap, which

maintains memory data retention in on-hook state, charged by a 5MΩ resistor . A higher load current would

discharge this capacitor and erase the memory contents.

2. The load will also be supplied in ringing mode.

3. When off-hook, the load current can be <5mA, provided it does not exceed this current at any time.

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