AD7863 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD7863 Datasheet PDF : 25 Pages
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AD7863
TIMING CHARACTERISTICS
VDD = 5 V ± 5%, AGND = DGND = 0 V, REF = Internal. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1, 2
tCONV
tACQ
Parallel Interface
t1
t2
t3
t4
t5 3
t6 4
t7
t8
A, B Versions
5.2
0.5
0
0
35
45
30
5
30
10
400
Unit
μs max
μs max
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
Test Conditions/Comments
Conversion time
Acquisition time
CS to RD setup time
CS to RD hold time
CONVST pulse width
RD pulse width
Data access time after falling edge of RD
Bus relinquish time after rising edge of RD
Time between consecutive reads
Quiet time
1 Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2 See Figure 2.
3 Measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.8 V or 2.0 V.
4 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
CONVST
BUSY
A0
CS
RD
DATA
t3
tCONV = 5.2µs
tACQ
t8
t1
t2
t7
t4
t5
VA1
t6
VA2
Figure 2. Timing Diagram
VB1
VB2
1.6mA
TO OUTPUT
PIN
50pF
200µA
Figure 3. Load Circuit for Access Time and Bus Relinquish Time
Rev. B | Page 5 of 24
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