AD7863 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
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Fabricante
AD7863 Datasheet PDF : 25 Pages
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AD7863
Parameter
REFERENCE INPUT/OUTPUT
REF IN Input Voltage Range
REF IN Input Current
REF OUT Output Voltage
REF OUT Error @ 25°C
REF OUT Error TMIN to TMAX
REF OUT Temperature Coefficient
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN5
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
DB11 to DB0
Floating-State Leakage Current
Floating-State Capacitance5
Output Coding
AD7863-10, AD7863-3
AD7863-2
CONVERSION RATE
Conversion Time
Mode 1 Operation
Mode 2 Operation6
Track/Hold Acquisition Time4, 7
POWER REQUIREMENTS
VDD
IDD
Normal Mode (Mode 1)
AD7863-10
AD7863-3
AD7863-2
Power-Down Mode (Mode 2)
IDD @ 25°C8
Power Dissipation
Normal Mode (Mode 1)
AD7863-10
AD7863-3
AD7863-2
Power-Down Mode @ 25°C
A Version1
B Version1
Unit
2.375 to 2.625
±100
2.5
±10
±20
25
2.375 to 2.625
±100
2.5
±10
±20
25
V
μA max
V nom
mV max
mV max
ppm/°C typ
2.4
2.4
V min
0.8
0.8
V max
±10
±10
μA max
10
10
pF max
4.0
4.0
V min
0.4
0.4
V max
±10
±10
μA max
10
10
pF max
Test Conditions/Comments
2.5 V ± 5%
VDD = 5 V ± 5%
VDD = 5 V ± 5%
ISOURCE = 200 μA
ISINK = 1.6 mA
Twos complement
Straight (natural) binary
5.2
5.2
μs max
For both channels
10.0
10.0
μs max
For both channels
0.5
0.5
μs max
5
5
V nom
±5% for specified performance
18
18
mA max
16
16
mA max
11
11
mA max
20
20
μA max
40 nA typ. Logic inputs = 0 V or VDD
94.50
84
57.75
105
94.50
84
57.75
105
mW max
mW max
mW max
μW max
VDD = 5.25 V, 70 mW typ
VDD = 5.25 V, 70 mW typ
VDD = 5.25 V, 45 mW typ
210 nW typ, VDD = 5.25 V
1 Temperature ranges are as follows: A Version and B Version, −40°C to +85°C.
2 Sample tested during initial release.
3 Applies to Mode 1 operation. See Operating Modes section.
4 See Terminology section.
5 Sample tested @ 25°C to ensure compliance.
6 This 10 μs includes the wake-up time from standby. This wake-up time is timed from the rising edge of CONVST, whereas conversion is timed from the falling edge of
CONVST, for a narrow CONVST pulse width the conversion time is effectively the wake-up time plus conversion time, 10 μs. This can be seen from Figure 6. Note that if
the CONVST pulse width is greater than 5.2 μs, the effective conversion time increases beyond 10 μs.
7 Performance measured through full channel (multiplexer, SHA, and ADC).
8 For best dynamic performance of the AD7863, ATE device testing has to be performed with power supply decoupling in place. In the AD7863 power-down mode of
operation, the leakage current associated with these decoupling capacitors is greater than that of the AD7863 supply current. Therefore, the 40 nA typical figure
shown is characterized and guaranteed by design figure, which reflects the supply current of the AD7863 without decoupling in place. The maximum figure shown in
the Conditions/Comments column reflects the AD7863 with supply decoupling in place—0.1 μF in parallel with 10 μF disc ceramic capacitors on the VDD pin and
2 × 0.1 μF disc ceramic capacitors on the VREF pin, in both cases to the AGND plane.
Rev. B | Page 4 of 24
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