ADSP-21061 Ver la hoja de datos (PDF) - Analog Devices

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ADSP-21061

Commercial Grade SHARC DSP Microcomputer

Analog Devices 

Table 2. Pin Descriptions (Continued)

ADSP-21061/ADSP-21061L

Pin

TFSx

RFSx

EBOOT

LBOOT

BMS

Type

I/O

I/O

I

I

I/O/T*

Function

Transmit Frame Sync (Serial Ports 0, 1).

Receive Frame Sync (Serial Ports 0, 1).

EPROM Boot Select. When EBOOT is high, the ADSP-21061 is configured for booting from an 8-bit EPROM.

When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See the table in the BMS pin

description below. This signal is a system configuration selection that should be hardwired.

Link Boot. Must be tied to GND.

Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1,

LBOOT = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates that no

booting will occur and that ADSP-21061 will begin executing instructions from external memory. See table

below. This input is a system configuration selection that should be hardwired. *Three-statable only in

EPROM boot mode (when BMS is an output).

EBOOT

1

0

0

LBOOT

0

0

0

BMS

Output

1(Input)

0 (Input)

Booting Mode

EPROM (Connect BMS to EPROM chip select.)

Host Processor.

No Booting. Processor executes from external memory.

CLKIN

I

Clock In. External clock input to the ADSP-21061. The instruction cycle rate is equal to CLKIN. CLKIN may

not be halted, changed, or operated below the minimum specified frequency.

RESET

I/A

Processor Reset. Resets the ADSP-21061 to a known state and begins program execution at the program

memory location specified by the hardware reset vector address. This input must be asserted (low) at

power-up.

TCK

I

Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.

TMS

I/S

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 k internal pull-up resistor.

TDI

I/S

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 k internal pull-up

resistor.

TDO

O

Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST

I/A

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held

low for proper operation of the ADSP-21061. TRST has a 20 k internal pull-up resistor.

EMU

O

Emulation Status. Must be connected to the ADSP-21061 EZ-ICE target board connector only. EMU has a

50 k internal pull-up resistor.

ICSA

O

Reserved. Leave unconnected.

VDD

P

Power Supply. (30 pins). See Operating Conditions (5 V) and Operating Conditions (3.3 V).

GND

G

Power Supply Return. (30 pins)

NC

Do Not Connect. Reserved pins which must be left open and unconnected.

A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open-Drain,

T = Three-State (when SBTS is asserted, or when the ADSP-21061 is a bus slave)

Rev. D | Page 11 of 52 | May 2013

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