ML6510CQ-80 Ver la hoja de datos (PDF) - Micro Linear Corporation

Número de pieza

componentes Descripción

Fabricante

ML6510CQ-80

Series Programmable Adaptive Clock Manager (PACMan™)

Micro Linear Corporation 

PIN DESCRIPTION

PIN NUMBER

32

NAME

ROMMSB

20

MDOUT

19

MDIN

21

MCLK

22

RESET

23

LOCK

28

CLKINH

29

CLKINL

16,14,9,7,

44, 42, 37, 35

18,12,11,5,

2, 40, 39, 33

3,31

25

4, 30, 24

15

8

43

36

17, 13, 10, 6,

1, 41, 38, 34

26

27

CLK[0–7]

FB[0–7]

AVCC[1–3]

AGND[1–3]

DVCC01

DVCC23

DVCC45

DVCC67

DGND[0–7]

RCLKL

RCLKH

ML6510

DESCRIPTION

MSB of the internal ROM address. Tie to GND if not used. See section on

Programming the ML6510.

Programming pin. See section on Programming the ML6510.

Programming pin. See section on Programming the ML6510.

Programming pin. See section on Programming the ML6510.

Reset all internal circuits. Asserted polarity is low.

Indicates when the PLL and deskew buffers have locked. Asserted polarity is

high.

Input clock pins. For TTL clock reference use CLKINH pin

shorted to the CLKINL pin. For PECL clock reference drive pins differentially.

Input clock type is selected by the CS bit in the shift register.

Clock outputs

Clock feedback inputs for the deskew buffers

Analog circuitry supply pins, separated from noisy digital supply pins to

provide isolation. All supplies are nominally +5V.

Analog circuitry ground pins

Digital supply pin for CLK0 and CLK1 output buffers. Nominally +5V.

Digital supply pin for CLK2 and CLK3 output buffers. Nominally +5V.

Digital supply pin for CLK4 and CLK5 output buffers. Nominally +5V.

Digital supply pin for CLK6 and CLK7 output buffers. Nominally +5V.

Digital ground pins for CLK [0–7] output buffers. Each clock output buffer has

its own ground pin to avoid crosstalk and ground bounce problems.

Differential reference clock output used to minimize

part-to-part skew when building clock trees with other PACMan

integrated circuits.

3

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